untitled.laf

上载硬部线学校课程设计

   PIN A0 IN JMP;
 END;
 SYM NAND2 GATE_T__4_I_3;
   PIN ZN0 OUT T__4;
   PIN A0 IN GATE_T__4_N_1;
   PIN A1 IN GATE_T__4_N_2;
 END;
 SYM INV GATE_T__4_I_2;
   PIN ZN0 OUT GATE_T__4_N_2;
   PIN A0 IN STA;
 END;
 SYM INV GATE_T__4_I_1;
   PIN ZN0 OUT GATE_T__4_N_1;
   PIN A0 IN LDA;
 END;
 SYM NAND2 GATE_T__5_I_3;
   PIN ZN0 OUT T__5;
   PIN A0 IN GATE_T__5_N_1;
   PIN A1 IN GATE_T__5_N_2;
 END;
 SYM INV GATE_T__5_I_2;
   PIN ZN0 OUT GATE_T__5_N_2;
   PIN A0 IN T__68;
 END;
 SYM INV GATE_T__5_I_1;
   PIN ZN0 OUT GATE_T__5_N_1;
   PIN A0 IN T__67;
 END;
 SYM NAND2 GATE_T__6_I_3;
   PIN ZN0 OUT T__6;
   PIN A0 IN GATE_T__6_N_1;
   PIN A1 IN GATE_T__6_N_2;
 END;
 SYM INV GATE_T__6_I_2;
   PIN ZN0 OUT GATE_T__6_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__6_I_1;
   PIN ZN0 OUT GATE_T__6_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM NAND2 GATE_T__7_I_3;
   PIN ZN0 OUT T__7;
   PIN A0 IN GATE_T__7_N_1;
   PIN A1 IN GATE_T__7_N_2;
 END;
 SYM INV GATE_T__7_I_2;
   PIN ZN0 OUT GATE_T__7_N_2;
   PIN A0 IN KWE2;
 END;
 SYM INV GATE_T__7_I_1;
   PIN ZN0 OUT GATE_T__7_N_1;
   PIN A0 IN KRD2;
 END;
 SYM NAND2 GATE_T__8_I_3;
   PIN ZN0 OUT T__8;
   PIN A0 IN GATE_T__8_N_1;
   PIN A1 IN GATE_T__8_N_2;
 END;
 SYM INV GATE_T__8_I_2;
   PIN ZN0 OUT GATE_T__8_N_2;
   PIN A0 IN T__63;
 END;
 SYM INV GATE_T__8_I_1;
   PIN ZN0 OUT GATE_T__8_N_1;
   PIN A0 IN T__62;
 END;
 SYM NAND2 GATE_T__9_I_3;
   PIN ZN0 OUT T__9;
   PIN A0 IN IN_W3_U1_Z0;
   PIN A1 IN LDA;
 END;
 SYM NAND2 GATE_T__10_I_3;
   PIN ZN0 OUT T__10;
   PIN A0 IN GATE_T__10_N_1;
   PIN A1 IN IN_W1_U1_Z0;
 END;
 SYM INV GATE_T__10_I_1;
   PIN ZN0 OUT GATE_T__10_N_1;
   PIN A0 IN T__61;
 END;
 SYM NAND2 GATE_T__11_I_3;
   PIN ZN0 OUT T__11;
   PIN A0 IN IN_W4_U1_Z0;
   PIN A1 IN STA;
 END;
 SYM NAND4 GATE_T__12_U1;
   PIN ZN0 OUT T__12;
   PIN A0 IN GATE_T__12_N_1;
   PIN A1 IN GATE_T__12_N_2;
   PIN A2 IN GATE_T__12_N_3;
   PIN A3 IN GATE_T__12_N_4;
 END;
 SYM INV GATE_T__12_I_1;
   PIN ZN0 OUT GATE_T__12_N_4;
   PIN A0 IN T__58;
 END;
 SYM INV GATE_T__12_U4;
   PIN ZN0 OUT GATE_T__12_N_3;
   PIN A0 IN LDA;
 END;
 SYM INV GATE_T__12_U3;
   PIN ZN0 OUT GATE_T__12_N_2;
   PIN A0 IN S2_COM_BLIF;
 END;
 SYM INV GATE_T__12_U2;
   PIN ZN0 OUT GATE_T__12_N_1;
   PIN A0 IN KLD2;
 END;
 SYM NAND2 GATE_T__13_I_3;
   PIN ZN0 OUT T__13;
   PIN A0 IN GATE_T__13_N_1;
   PIN A1 IN IN_IR5_U1_Z0;
 END;
 SYM INV GATE_T__13_I_1;
   PIN ZN0 OUT GATE_T__13_N_1;
   PIN A0 IN IN_IR4_U1_Z0;
 END;
 SYM NAND2 GATE_T__14_I_3;
   PIN ZN0 OUT T__14;
   PIN A0 IN GATE_T__14_N_1;
   PIN A1 IN GATE_T__14_N_2;
 END;
 SYM INV GATE_T__14_I_2;
   PIN ZN0 OUT GATE_T__14_N_2;
   PIN A0 IN T__56;
 END;
 SYM INV GATE_T__14_I_1;
   PIN ZN0 OUT GATE_T__14_N_1;
   PIN A0 IN T__55;
 END;
 SYM NAND2 GATE_T__15_I_3;
   PIN ZN0 OUT T__15;
   PIN A0 IN GATE_T__15_N_1;
   PIN A1 IN IN_W1_U1_Z0;
 END;
 SYM INV GATE_T__15_I_1;
   PIN ZN0 OUT GATE_T__15_N_1;
   PIN A0 IN T__57;
 END;
 SYM NAND2 GATE_T__16_I_3;
   PIN ZN0 OUT T__16;
   PIN A0 IN GATE_T__16_N_1;
   PIN A1 IN IN_W4_U1_Z0;
 END;
 SYM INV GATE_T__16_I_1;
   PIN ZN0 OUT GATE_T__16_N_1;
   PIN A0 IN STO_Q_BLIF;
 END;
 SYM NAND2 GATE_T__17_I_3;
   PIN ZN0 OUT T__17;
   PIN A0 IN GATE_T__17_N_1;
   PIN A1 IN IN_W4_U1_Z0;
 END;
 SYM INV GATE_T__17_I_1;
   PIN ZN0 OUT GATE_T__17_N_1;
   PIN A0 IN T__53;
 END;
 SYM NAND2 GATE_T__18_I_3;
   PIN ZN0 OUT T__18;
   PIN A0 IN GATE_T__18_N_1;
   PIN A1 IN IN_W2_U1_Z0;
 END;
 SYM INV GATE_T__18_I_1;
   PIN ZN0 OUT GATE_T__18_N_1;
   PIN A0 IN T__54;
 END;
 SYM NAND4 GATE_T__19_U1;
   PIN ZN0 OUT T__19;
   PIN A0 IN GATE_T__19_N_1;
   PIN A1 IN GATE_T__19_N_2;
   PIN A2 IN GATE_T__19_N_3;
   PIN A3 IN GATE_T__19_N_4;
 END;
 SYM INV GATE_T__19_I_1;
   PIN ZN0 OUT GATE_T__19_N_4;
   PIN A0 IN T__52;
 END;
 SYM INV GATE_T__19_U4;
   PIN ZN0 OUT GATE_T__19_N_3;
   PIN A0 IN LDA;
 END;
 SYM INV GATE_T__19_U3;
   PIN ZN0 OUT GATE_T__19_N_2;
   PIN A0 IN S2_COM_BLIF;
 END;
 SYM INV GATE_T__19_U2;
   PIN ZN0 OUT GATE_T__19_N_1;
   PIN A0 IN KLD2;
 END;
 SYM NAND2 GATE_T__20_I_3;
   PIN ZN0 OUT T__20;
   PIN A0 IN GATE_T__20_N_1;
   PIN A1 IN IN_IR5_U1_Z0;
 END;
 SYM INV GATE_T__20_I_1;
   PIN ZN0 OUT GATE_T__20_N_1;
   PIN A0 IN IN_IR4_U1_Z0;
 END;
 SYM NAND3 GATE_T__21_I_1;
   PIN ZN0 OUT T__21;
   PIN A0 IN GATE_T__21_N_1;
   PIN A1 IN GATE_T__21_N_2;
   PIN A2 IN GATE_T__21_N_3;
 END;
 SYM INV GATE_T__21_I_3;
   PIN ZN0 OUT GATE_T__21_N_3;
   PIN A0 IN STA;
 END;
 SYM INV GATE_T__21_U3;
   PIN ZN0 OUT GATE_T__21_N_2;
   PIN A0 IN S2_COM_BLIF;
 END;
 SYM INV GATE_T__21_I_2;
   PIN ZN0 OUT GATE_T__21_N_1;
   PIN A0 IN T__51;
 END;
 SYM NAND2 GATE_T__22_I_3;
   PIN ZN0 OUT T__22;
   PIN A0 IN GATE_T__22_N_1;
   PIN A1 IN IN_IR5_U1_Z0;
 END;
 SYM INV GATE_T__22_I_1;
   PIN ZN0 OUT GATE_T__22_N_1;
   PIN A0 IN IN_IR4_U1_Z0;
 END;
 SYM NAND2 GATE_T__23_I_3;
   PIN ZN0 OUT T__23;
   PIN A0 IN GATE_T__23_N_1;
   PIN A1 IN GATE_T__23_N_2;
 END;
 SYM INV GATE_T__23_I_2;
   PIN ZN0 OUT GATE_T__23_N_2;
   PIN A0 IN T__49;
 END;
 SYM INV GATE_T__23_I_1;
   PIN ZN0 OUT GATE_T__23_N_1;
   PIN A0 IN S2_COM_BLIF;
 END;
 SYM NAND2 GATE_T__24_I_3;
   PIN ZN0 OUT T__24;
   PIN A0 IN GATE_T__24_N_1;
   PIN A1 IN IN_IR5_U1_Z0;
 END;
 SYM INV GATE_T__24_I_1;
   PIN ZN0 OUT GATE_T__24_N_1;
   PIN A0 IN IN_IR4_U1_Z0;
 END;
 SYM NAND2 GATE_T__25_I_3;
   PIN ZN0 OUT T__25;
   PIN A0 IN GATE_T__25_N_1;
   PIN A1 IN GATE_T__25_N_2;
 END;
 SYM INV GATE_T__25_I_2;
   PIN ZN0 OUT GATE_T__25_N_2;
   PIN A0 IN T__44;
 END;
 SYM INV GATE_T__25_I_1;
   PIN ZN0 OUT GATE_T__25_N_1;
   PIN A0 IN T__43;
 END;
 SYM NAND2 GATE_T__26_I_3;
   PIN ZN0 OUT T__26;
   PIN A0 IN GATE_T__26_N_1;
   PIN A1 IN GATE_T__26_N_2;
 END;
 SYM INV GATE_T__26_I_2;
   PIN ZN0 OUT GATE_T__26_N_2;
   PIN A0 IN T__46;
 END;
 SYM INV GATE_T__26_I_1;
   PIN ZN0 OUT GATE_T__26_N_1;
   PIN A0 IN T__45;
 END;
 SYM NAND3 GATE_T__27_I_1;
   PIN ZN0 OUT T__27;
   PIN A0 IN GATE_T__27_N_1;
   PIN A1 IN GATE_T__27_N_2;
   PIN A2 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__27_U3;
   PIN ZN0 OUT GATE_T__27_N_2;
   PIN A0 IN KRD2;
 END;
 SYM INV GATE_T__27_I_2;
   PIN ZN0 OUT GATE_T__27_N_1;
   PIN A0 IN KWE2;
 END;
 SYM NAND4 GATE_T__28_U1;
   PIN ZN0 OUT T__28;
   PIN A0 IN GATE_T__28_N_1;
   PIN A1 IN GATE_T__28_N_2;
   PIN A2 IN GATE_T__28_N_3;
   PIN A3 IN GATE_T__28_N_4;
 END;
 SYM INV GATE_T__28_I_1;
   PIN ZN0 OUT GATE_T__28_N_4;
   PIN A0 IN T__37;
 END;
 SYM INV GATE_T__28_U4;
   PIN ZN0 OUT GATE_T__28_N_3;
   PIN A0 IN JMP;
 END;
 SYM INV GATE_T__28_U3;
   PIN ZN0 OUT GATE_T__28_N_2;
   PIN A0 IN STA;
 END;
 SYM INV GATE_T__28_U2;
   PIN ZN0 OUT GATE_T__28_N_1;
   PIN A0 IN KRR2;
 END;
 SYM NAND2 GATE_T__29_I_3;
   PIN ZN0 OUT T__29;
   PIN A0 IN GATE_T__29_N_1;
   PIN A1 IN GATE_T__29_N_2;
 END;
 SYM INV GATE_T__29_I_2;
   PIN ZN0 OUT GATE_T__29_N_2;
   PIN A0 IN T__39;
 END;
 SYM INV GATE_T__29_I_1;
   PIN ZN0 OUT GATE_T__29_N_1;
   PIN A0 IN T__38;
 END;
 SYM NAND2 GATE_T__30_I_3;
   PIN ZN0 OUT T__30;
   PIN A0 IN GATE_T__30_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__30_I_1;
   PIN ZN0 OUT GATE_T__30_N_1;
   PIN A0 IN RUN_Q_BLIF;
 END;
 SYM NAND2 GATE_T__31_I_3;
   PIN ZN0 OUT T__31;
   PIN A0 IN GATE_T__31_N_1;
   PIN A1 IN GATE_T__31_N_2;
 END;
 SYM INV GATE_T__31_I_2;
   PIN ZN0 OUT GATE_T__31_N_2;
   PIN A0 IN T__32;
 END;
 SYM INV GATE_T__31_I_1;
   PIN ZN0 OUT GATE_T__31_N_1;
   PIN A0 IN STO_Q_BLIF;
 END;
 SYM AND2 GATE_T__32_U1;
   PIN Z0 OUT T__32;
   PIN A0 IN RUN_Q_BLIF;
   PIN A1 IN IN_W4_U1_Z0;
 END;
 SYM INV GATE_T__33_I_1;
   PIN ZN0 OUT GATE_T__33_N_1;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM AND2 GATE_T__33_U1;
   PIN Z0 OUT T__33;
   PIN A0 IN GATE_T__33_N_1;
   PIN A1 IN IN_MF_U1_Z0;
 END;
 SYM INV GATE_T__34_I_1;
   PIN ZN0 OUT GATE_T__34_N_1;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM AND2 GATE_T__34_U1;
   PIN Z0 OUT T__34;
   PIN A0 IN GATE_T__34_N_1;
   PIN A1 IN IN_MF_U1_Z0;
 END;
 SYM AND2 GATE_T__35_U1;
   PIN Z0 OUT T__35;
   PIN A0 IN IN_W1_U1_Z0;
   PIN A1 IN T__27;
 END;
 SYM AND2 GATE_T__36_U1;
   PIN Z0 OUT T__36;
   PIN A0 IN IN_W2_U1_Z0;
   PIN A1 IN T__28;
 END;
 SYM AND3 GATE_T__37_I_4;
   PIN Z0 OUT T__37;
   PIN A0 IN T__74;
   PIN A1 IN T__29;
   PIN A2 IN T__75;
 END;
 SYM AND4 GATE_T__38_U1;
   PIN Z0 OUT T__38;
   PIN A0 IN GATE_T__38_N_1;
   PIN A1 IN GATE_T__38_N_2;
   PIN A2 IN IN_IR6_U1_Z0;
   PIN A3 IN IN_IR5_U1_Z0;
 END;
 SYM INV GATE_T__38_U3;
   PIN ZN0 OUT GATE_T__38_N_2;
   PIN A0 IN IN_IR4_U1_Z0;
 END;