untitled.laf

上载硬部线学校课程设计

  NET GATE_T__113_N_2  SRC GATE_T__113_I_2.ZN0  DST GATE_T__113_U1.A1 ;
  NET GATE_T__114_N_1  SRC GATE_T__114_I_1.ZN0  DST GATE_T__114_U1.A0 ;
  NET GATE_T__115_N_1  SRC GATE_T__115_I_1.ZN0  DST GATE_T__115_U1.A0 ;
  NET GATE_T__115_N_2  SRC GATE_T__115_I_2.ZN0  DST GATE_T__115_U1.A1 ;
  NET GATE_T__116_N_1  SRC GATE_T__116_I_1.ZN0  DST GATE_T__116_U1.A0 ;
  NET GATE_T__117_N_1  SRC GATE_T__117_I_1.ZN0  DST GATE_T__117_U1.A0 ;
  NET GATE_T__118_N_1  SRC GATE_T__118_I_1.ZN0  DST GATE_T__118_U1.A0 ;
  NET GATE_T__119_N_1  SRC GATE_T__119_I_1.ZN0  DST GATE_T__119_U1.A0 ;
  NET GATE_T__119_N_2  SRC GATE_T__119_I_2.ZN0  DST GATE_T__119_U1.A1 ;
  NET GATE_T__120_N_1  SRC GATE_T__120_I_1.ZN0  DST GATE_T__120_U1.A0 ;
  NET IN_CLR_U1_Z0  SRC IN_CLR_U1_$1I45.Z0  DST GATE_RUN_D_REG_U1.A0 GATE_STO_D_REG_U1.A0 GATE_T__33_I_1.A0 GATE_T__34_I_1.A0 ;
  NET IN_MF_U1_Z0  SRC IN_MF_U1_$1I45.Z0  DST GATE_T__33_U1.A1 GATE_T__34_U1.A1 ;
  NET IN_T1_U1_Z0  SRC IN_T1_U1_$1I45.Z0  DST GATE_RUN_C_I_1.A0 GATE_STO_C_I_1.A0 ;
  NET IN_W1_U1_Z0  SRC IN_W1_U1_$1I45.Z0  DST GATE_T__10_I_3.A1 GATE_T__15_I_3.A1 GATE_T__35_U1.A0 GATE_T__42_U1.A0 GATE_T__56_I_2.A0 GATE_T__60_U1.A0 GATE_T__67_I_4.A1 GATE_T__72_I_4.A1 ;
  NET IN_W2_U1_Z0  SRC IN_W2_U1_$1I45.Z0  DST GATE_LDDR1_U1.A0 GATE_T__18_I_3.A1 GATE_T__36_U1.A0 GATE_T__41_U1.A0 GATE_T__65_U1.A0 GATE_T__73_U1.A0 ;
  NET IN_W3_U1_Z0  SRC IN_W3_U1_$1I45.Z0  DST GATE_LDER_U1.A0 GATE_T__9_I_3.A0 GATE_T__47_U1.A0 GATE_T__56_I_1.A0 GATE_T__59_U1.A0 ;
  NET IN_W4_U1_Z0  SRC IN_W4_U1_$1I45.Z0  DST GATE_LDPC_U1.A0 GATE_M4_U1.A0 GATE_AR1_INC_U1.A0 GATE_M3_I_4.A2 GATE_WRD_U1.A0 GATE_T__11_I_3.A0 GATE_T__16_I_3.A1 GATE_T__17_I_3.A1 GATE_T__32_U1.A1 GATE_T__40_U1.A0 GATE_T__48_U1.A0 GATE_T__64_U1.A2 GATE_T__68_I_4.A2 GATE_T__112_I_4.A2 ;
  NET IN_IR4_U1_Z0  SRC IN_IR4_U1_$1I45.Z0  DST GATE_T__13_I_1.A0 GATE_T__20_I_1.A0 GATE_T__22_I_1.A0 GATE_T__24_I_1.A0 GATE_T__38_U3.A0 GATE_T__39_U1.A3 GATE_T__76_I_1.A0 GATE_T__82_U1.A1 GATE_T__95_I_1.A0 GATE_T__102_I_2.A0 GATE_T__106_U1.A1 GATE_T__110_I_4.A2 GATE_T__113_I_2.A0 GATE_T__117_U1.A1 ;
  NET IN_IR5_U1_Z0  SRC IN_IR5_U1_$1I45.Z0  DST GATE_S1_U2.A0 GATE_T__13_I_3.A1 GATE_T__20_I_3.A1 GATE_T__22_I_3.A1 GATE_T__24_I_3.A1 GATE_T__38_U1.A3 GATE_T__39_U3.A0 GATE_T__76_U1.A1 GATE_T__82_I_1.A0 GATE_T__95_U1.A1 GATE_T__102_I_1.A0 GATE_T__106_I_1.A0 GATE_T__110_I_2.A0 GATE_T__113_I_1.A0 GATE_T__117_I_1.A0 ;
  NET IN_IR6_U1_Z0  SRC IN_IR6_U1_$1I45.Z0  DST GATE_T__38_U1.A2 GATE_T__39_U2.A0 GATE_T__77_U1.A1 GATE_T__79_I_2.A0 GATE_T__83_I_2.A0 GATE_T__86_I_2.A0 GATE_T__89_I_2.A0 GATE_T__92_I_2.A0 GATE_T__96_I_2.A0 GATE_T__99_I_2.A0 GATE_T__103_U1.A1 GATE_T__107_U1.A1 GATE_T__110_U3.A0 GATE_T__114_I_1.A0 GATE_T__118_I_1.A0 ;
  NET IN_IR7_U1_Z0  SRC IN_IR7_U1_$1I45.Z0  DST GATE_T__38_U2.A0 GATE_T__39_U1.A2 GATE_T__77_I_1.A0 GATE_T__79_I_1.A0 GATE_T__83_I_1.A0 GATE_T__86_I_1.A0 GATE_T__89_I_1.A0 GATE_T__92_I_1.A0 GATE_T__96_I_1.A0 GATE_T__99_I_1.A0 GATE_T__103_I_1.A0 GATE_T__107_I_1.A0 GATE_T__111_I_4.A2 GATE_T__114_U1.A1 GATE_T__118_U1.A1 ;
  NET IN_SWC_U1_Z0  SRC IN_SWC_U1_$1I45.Z0  DST GATE_KRR2_U1.A3 GATE_KRD2_U2.A0 GATE_KWE2_U2.A0 GATE_KLD2_U2.A0 GATE_T__44_I_1.A0 GATE_T__46_U1.A1 GATE_T__62_I_4.A2 GATE_T__63_I_2.A0 GATE_T__64_U3.A0 GATE_T__67_I_2.A0 GATE_T__68_I_4.A1 GATE_T__69_U3.A0 GATE_T__70_U2.A0 GATE_T__75_I_1.A0 GATE_T__78_I_1.A0 GATE_T__81_I_1.A0 GATE_T__85_I_1.A0 GATE_T__88_I_1.A0 GATE_T__91_I_1.A0 GATE_T__94_I_1.A0 GATE_T__98_I_1.A0 GATE_T__101_I_1.A0 GATE_T__105_I_1.A0 GATE_T__109_I_1.A0 GATE_T__112_I_2.A0 GATE_T__116_I_1.A0 GATE_T__120_I_1.A0 ;
  NET IN_SWB_U1_Z0  SRC IN_SWB_U1_$1I45.Z0  DST GATE_KRR2_U2.A0 GATE_KRD2_U3.A0 GATE_KWE2_U1.A3 GATE_KLD2_U1.A2 GATE_T__6_I_1.A0 GATE_T__44_U1.A1 GATE_T__46_I_1.A0 GATE_T__62_U3.A0 GATE_T__63_I_4.A2 GATE_T__69_U4.A0 GATE_T__70_U3.A0 GATE_T__74_I_1.A0 GATE_T__80_I_1.A0 GATE_T__84_I_1.A0 GATE_T__87_I_1.A0 GATE_T__90_I_1.A0 GATE_T__93_I_1.A0 GATE_T__97_I_1.A0 GATE_T__100_I_1.A0 GATE_T__104_I_1.A0 GATE_T__108_I_1.A0 GATE_T__111_U3.A0 GATE_T__115_I_1.A0 GATE_T__119_I_1.A0 ;
  NET IN_SWA_U1_Z0  SRC IN_SWA_U1_$1I45.Z0  DST GATE_KRR2_U3.A0 GATE_KRD2_U1.A3 GATE_KWE2_U3.A0 GATE_KLD2_U1.A3 GATE_T__6_I_2.A0 GATE_T__43_I_1.A0 GATE_T__62_I_2.A0 GATE_T__63_I_4.A1 GATE_T__69_I_1.A0 GATE_T__70_U4.A0 GATE_T__74_I_2.A0 GATE_T__80_I_2.A0 GATE_T__84_I_2.A0 GATE_T__87_I_2.A0 GATE_T__90_I_2.A0 GATE_T__93_I_2.A0 GATE_T__97_I_2.A0 GATE_T__100_I_2.A0 GATE_T__104_I_2.A0 GATE_T__108_I_2.A0 GATE_T__111_I_2.A0 GATE_T__115_I_2.A0 GATE_T__119_I_2.A0 ;
  NET IN_C_U1_Z0  SRC IN_C_U1_$1I45.Z0  DST GATE_PC_ADD_U1.A0 GATE_T__71_I_4.A1 ;
  NET OUT_LDIR_U1_XO0 EXT  SRC OUT_LDIR_U1_$1I42.XO0 ;
  NET OUT_LDPC_U1_XO0 EXT  SRC OUT_LDPC_U1_$1I42.XO0 ;
  NET OUT_PC_ADD_U1_XO0 EXT  SRC OUT_PC_ADD_U1_$1I42.XO0 ;
  NET OUT_M4_U1_XO0 EXT  SRC OUT_M4_U1_$1I42.XO0 ;
  NET OUT_LDAR1_U1_XO0 EXT  SRC OUT_LDAR1_U1_$1I42.XO0 ;
  NET OUT_AR1_INC_U1_XO0 EXT  SRC OUT_AR1_INC_U1_$1I42.XO0 ;
  NET OUT_M3_U1_XO0 EXT  SRC OUT_M3_U1_$1I42.XO0 ;
  NET OUT_CEL_U1_XO0 EXT  SRC OUT_CEL_U1_$1I42.XO0 ;
  NET OUT_LRW_U1_XO0 EXT  SRC OUT_LRW_U1_$1I42.XO0 ;
  NET OUT_LDER_U1_XO0 EXT  SRC OUT_LDER_U1_$1I42.XO0 ;
  NET OUT_SW_BUS_U1_XO0 EXT  SRC OUT_SW_BUS_U1_$1I42.XO0 ;
  NET OUT_RS_BUS_U1_XO0 EXT  SRC OUT_RS_BUS_U1_$1I42.XO0 ;
  NET OUT_WRD_U1_XO0 EXT  SRC OUT_WRD_U1_$1I42.XO0 ;
  NET OUT_LDDR1_U1_XO0 EXT  SRC OUT_LDDR1_U1_$1I42.XO0 ;
  NET OUT_S1_U1_XO0 EXT  SRC OUT_S1_U1_$1I42.XO0 ;
  NET OUT_S0_U1_XO0 EXT  SRC OUT_S0_U1_$1I42.XO0 ;
  NET OUT_ALU_BUS_U1_XO0 EXT  SRC OUT_ALU_BUS_U1_$1I42.XO0 ;
  NET OUT_TJ_U1_XO0 EXT  SRC OUT_TJ_U1_$1I42.XO0 ;
  NET OUT_SKIP_U1_XO0 EXT  SRC OUT_SKIP_U1_$1I42.XO0 ;
  NET OUT_S2_U1_XO0 EXT  SRC OUT_S2_U1_$1I42.XO0 ;
 SYM FD11 FF_RUN_U1  ;
   PIN Q0 OUT RUN_Q_BLIF;
   PIN CLK IN RUN_C;
   PIN D0 IN RUN_D_REG;
 END;
 SYM FD11 FF_STO_U1  ;
   PIN Q0 OUT STO_Q_BLIF;
   PIN CLK IN STO_C;
   PIN D0 IN STO_D_REG;
 END;
 SYM NAND2 GATE_LDIR_I_3;
   PIN ZN0 OUT LDIR_COM_BLIF;
   PIN A0 IN GATE_LDIR_N_1;
   PIN A1 IN GATE_LDIR_N_2;
 END;
 SYM INV GATE_LDIR_I_2;
   PIN ZN0 OUT GATE_LDIR_N_2;
   PIN A0 IN T__73;
 END;
 SYM INV GATE_LDIR_I_1;
   PIN ZN0 OUT GATE_LDIR_N_1;
   PIN A0 IN T__72;
 END;
 SYM AND2 GATE_LDPC_U1;
   PIN Z0 OUT LDPC_COM_BLIF;
   PIN A0 IN IN_W4_U1_Z0;
   PIN A1 IN T__1;
 END;
 SYM AND4 GATE_PC_ADD_U1;
   PIN Z0 OUT PC_ADD_COM_BLIF;
   PIN A0 IN IN_C_U1_Z0;
   PIN A1 IN T__112;
   PIN A2 IN T__111;
   PIN A3 IN T__110;
 END;
 SYM AND2 GATE_M4_U1;
   PIN Z0 OUT M4_COM_BLIF;
   PIN A0 IN IN_W4_U1_Z0;
   PIN A1 IN T__3;
 END;
 SYM NAND3 GATE_LDAR1_I_1;
   PIN ZN0 OUT LDAR1_COM_BLIF;
   PIN A0 IN GATE_LDAR1_N_1;
   PIN A1 IN GATE_LDAR1_N_2;
   PIN A2 IN GATE_LDAR1_N_3;
 END;
 SYM INV GATE_LDAR1_I_3;
   PIN ZN0 OUT GATE_LDAR1_N_3;
   PIN A0 IN T__65;
 END;
 SYM INV GATE_LDAR1_U3;
   PIN ZN0 OUT GATE_LDAR1_N_2;
   PIN A0 IN T__64;
 END;
 SYM INV GATE_LDAR1_I_2;
   PIN ZN0 OUT GATE_LDAR1_N_1;
   PIN A0 IN T__66;
 END;
 SYM AND2 GATE_AR1_INC_U1;
   PIN Z0 OUT AR1_INC_COM_BLIF;
   PIN A0 IN IN_W4_U1_Z0;
   PIN A1 IN T__7;
 END;
 SYM AND3 GATE_M3_I_4;
   PIN Z0 OUT M3_COM_BLIF;
   PIN A0 IN GATE_M3_N_1;
   PIN A1 IN T__8;
   PIN A2 IN IN_W4_U1_Z0;
 END;
 SYM INV GATE_M3_I_2;
   PIN ZN0 OUT GATE_M3_N_1;
   PIN A0 IN STO_Q_BLIF;
 END;
 SYM AND3 GATE_CEL_I_4;
   PIN Z0 OUT CEL_COM_BLIF;
   PIN A0 IN T__9;
   PIN A1 IN T__11;
   PIN A2 IN T__10;
 END;
 SYM NAND2 GATE_LRW_I_3;
   PIN ZN0 OUT LRW_COM_BLIF;
   PIN A0 IN GATE_LRW_N_1;
   PIN A1 IN GATE_LRW_N_2;
 END;
 SYM INV GATE_LRW_I_2;
   PIN ZN0 OUT GATE_LRW_N_2;
   PIN A0 IN T__60;
 END;
 SYM INV GATE_LRW_I_1;
   PIN ZN0 OUT GATE_LRW_N_1;
   PIN A0 IN T__59;
 END;
 SYM AND2 GATE_LDER_U1;
   PIN Z0 OUT LDER_COM_BLIF;
   PIN A0 IN IN_W3_U1_Z0;
   PIN A1 IN T__12;
 END;
 SYM AND2 GATE_SW_BUS_U1;
   PIN Z0 OUT SW_BUS_COM_BLIF;
   PIN A0 IN T__16;
   PIN A1 IN T__14;
 END;
 SYM AND2 GATE_RS_BUS_U1;
   PIN Z0 OUT RS_BUS_COM_BLIF;
   PIN A0 IN T__18;
   PIN A1 IN T__17;
 END;
 SYM AND2 GATE_WRD_U1;
   PIN Z0 OUT WRD_COM_BLIF;
   PIN A0 IN IN_W4_U1_Z0;
   PIN A1 IN T__19;
 END;
 SYM AND2 GATE_LDDR1_U1;
   PIN Z0 OUT LDDR1_COM_BLIF;
   PIN A0 IN IN_W2_U1_Z0;
   PIN A1 IN T__21;
 END;
 SYM AND4 GATE_S1_U1;
   PIN Z0 OUT S1_COM_BLIF;
   PIN A0 IN GATE_S1_N_1;
   PIN A1 IN T__88;
   PIN A2 IN T__87;
   PIN A3 IN T__86;
 END;
 SYM INV GATE_S1_U2;
   PIN ZN0 OUT GATE_S1_N_1;
   PIN A0 IN IN_IR5_U1_Z0;
 END;
 SYM NAND2 GATE_S0_I_3;
   PIN ZN0 OUT S0_COM_BLIF;
   PIN A0 IN GATE_S0_N_1;
   PIN A1 IN GATE_S0_N_2;
 END;
 SYM INV GATE_S0_I_2;
   PIN ZN0 OUT GATE_S0_N_2;
   PIN A0 IN T__50;
 END;
 SYM INV GATE_S0_I_1;
   PIN ZN0 OUT GATE_S0_N_1;
   PIN A0 IN STA;
 END;
 SYM NAND2 GATE_ALU_BUS_I_3;
   PIN ZN0 OUT ALU_BUS_COM_BLIF;
   PIN A0 IN GATE_ALU_BUS_N_1;
   PIN A1 IN GATE_ALU_BUS_N_2;
 END;
 SYM INV GATE_ALU_BUS_I_2;
   PIN ZN0 OUT GATE_ALU_BUS_N_2;
   PIN A0 IN T__48;
 END;
 SYM INV GATE_ALU_BUS_I_1;
   PIN ZN0 OUT GATE_ALU_BUS_N_1;
   PIN A0 IN T__47;
 END;
 SYM NAND3 GATE_TJ_I_1;
   PIN ZN0 OUT TJ_COM_BLIF;
   PIN A0 IN GATE_TJ_N_1;
   PIN A1 IN GATE_TJ_N_2;
   PIN A2 IN GATE_TJ_N_3;
 END;
 SYM INV GATE_TJ_I_3;
   PIN ZN0 OUT GATE_TJ_N_3;
   PIN A0 IN T__41;
 END;
 SYM INV GATE_TJ_U3;
   PIN ZN0 OUT GATE_TJ_N_2;
   PIN A0 IN T__40;
 END;
 SYM INV GATE_TJ_I_2;
   PIN ZN0 OUT GATE_TJ_N_1;
   PIN A0 IN T__42;
 END;
 SYM NAND2 GATE_SKIP_I_3;
   PIN ZN0 OUT SKIP_COM_BLIF;
   PIN A0 IN GATE_SKIP_N_1;
   PIN A1 IN GATE_SKIP_N_2;
 END;
 SYM INV GATE_SKIP_I_2;
   PIN ZN0 OUT GATE_SKIP_N_2;
   PIN A0 IN T__36;
 END;
 SYM INV GATE_SKIP_I_1;
   PIN ZN0 OUT GATE_SKIP_N_1;
   PIN A0 IN T__35;
 END;
 SYM AND4 GATE_KRR2_U1;
   PIN Z0 OUT KRR2;
   PIN A0 IN GATE_KRR2_N_1;
   PIN A1 IN GATE_KRR2_N_2;
   PIN A2 IN STO_Q_BLIF;
   PIN A3 IN IN_SWC_U1_Z0;
 END;
 SYM INV GATE_KRR2_U3;
   PIN ZN0 OUT GATE_KRR2_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_KRR2_U2;
   PIN ZN0 OUT GATE_KRR2_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND4 GATE_KRD2_U1;
   PIN Z0 OUT KRD2;
   PIN A0 IN GATE_KRD2_N_1;
   PIN A1 IN GATE_KRD2_N_2;
   PIN A2 IN STO_Q_BLIF;
   PIN A3 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_KRD2_U3;
   PIN ZN0 OUT GATE_KRD2_N_2;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM INV GATE_KRD2_U2;
   PIN ZN0 OUT GATE_KRD2_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND4 GATE_KWE2_U1;
   PIN Z0 OUT KWE2;
   PIN A0 IN GATE_KWE2_N_1;
   PIN A1 IN GATE_KWE2_N_2;
   PIN A2 IN STO_Q_BLIF;
   PIN A3 IN IN_SWB_U1_Z0;
 END;
 SYM INV GATE_KWE2_U3;
   PIN ZN0 OUT GATE_KWE2_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_KWE2_U2;
   PIN ZN0 OUT GATE_KWE2_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND4 GATE_KLD2_U1;
   PIN Z0 OUT KLD2;
   PIN A0 IN GATE_KLD2_N_1;
   PIN A1 IN STO_Q_BLIF;
   PIN A2 IN IN_SWB_U1_Z0;
   PIN A3 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_KLD2_U2;
   PIN ZN0 OUT GATE_KLD2_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND4 GATE_S2_U1;
   PIN Z0 OUT S2_COM_BLIF;
   PIN A0 IN T__98;
   PIN A1 IN T__97;
   PIN A2 IN T__96;
   PIN A3 IN T__95;
 END;
 SYM AND4 GATE_LDA_U1;
   PIN Z0 OUT LDA;
   PIN A0 IN T__109;
   PIN A1 IN T__108;
   PIN A2 IN T__107;
   PIN A3 IN T__106;
 END;
 SYM AND4 GATE_STA_U1;
   PIN Z0 OUT STA;
   PIN A0 IN T__105;
   PIN A1 IN T__104;
   PIN A2 IN T__103;
   PIN A3 IN T__102;
 END;
 SYM AND4 GATE_JMP_U1;
   PIN Z0 OUT JMP;
   PIN A0 IN T__116;
   PIN A1 IN T__115;
   PIN A2 IN T__114;
   PIN A3 IN T__113;
 END;
 SYM NAND2 GATE_RUN_C_I_3;
   PIN ZN0 OUT RUN_C;
   PIN A0 IN GATE_RUN_C_N_1;
   PIN A1 IN GATE_RUN_C_N_2;
 END;
 SYM INV GATE_RUN_C_I_2;
   PIN ZN0 OUT GATE_RUN_C_N_2;
   PIN A0 IN T__34;
 END;
 SYM INV GATE_RUN_C_I_1;
   PIN ZN0 OUT GATE_RUN_C_N_1;
   PIN A0 IN IN_T1_U1_Z0;
 END;
 SYM NAND2 GATE_STO_C_I_3;
   PIN ZN0 OUT STO_C;
   PIN A0 IN GATE_STO_C_N_1;
   PIN A1 IN GATE_STO_C_N_2;
 END;
 SYM INV GATE_STO_C_I_2;
   PIN ZN0 OUT GATE_STO_C_N_2;
   PIN A0 IN T__33;
 END;
 SYM INV GATE_STO_C_I_1;
   PIN ZN0 OUT GATE_STO_C_N_1;
   PIN A0 IN IN_T1_U1_Z0;
 END;
 SYM AND2 GATE_RUN_D_REG_U1;
   PIN Z0 OUT RUN_D_REG;
   PIN A0 IN IN_CLR_U1_Z0;
   PIN A1 IN T__30;
 END;
 SYM AND2 GATE_STO_D_REG_U1;
   PIN Z0 OUT STO_D_REG;
   PIN A0 IN IN_CLR_U1_Z0;
   PIN A1 IN T__31;
 END;
 SYM NAND2 GATE_T__0_I_3;
   PIN ZN0 OUT T__0;
   PIN A0 IN GATE_T__0_N_1;
   PIN A1 IN GATE_T__0_N_2;
 END;
 SYM INV GATE_T__0_I_2;
   PIN ZN0 OUT GATE_T__0_N_2;
   PIN A0 IN KLD2;
 END;
 SYM INV GATE_T__0_I_1;
   PIN ZN0 OUT GATE_T__0_N_1;
   PIN A0 IN KRR2;
 END;
 SYM NAND2 GATE_T__1_I_3;
   PIN ZN0 OUT T__1;
   PIN A0 IN GATE_T__1_N_1;
   PIN A1 IN GATE_T__1_N_2;
 END;
 SYM INV GATE_T__1_I_2;
   PIN ZN0 OUT GATE_T__1_N_2;
   PIN A0 IN T__70;
 END;
 SYM INV GATE_T__1_I_1;
   PIN ZN0 OUT GATE_T__1_N_1;
   PIN A0 IN JMP;
 END;
 SYM NAND2 GATE_T__2_I_3;
   PIN ZN0 OUT T__2;
   PIN A0 IN GATE_T__2_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__2_I_1;
   PIN ZN0 OUT GATE_T__2_N_1;
   PIN A0 IN T__71;
 END;
 SYM NAND2 GATE_T__3_I_3;
   PIN ZN0 OUT T__3;
   PIN A0 IN GATE_T__3_N_1;
   PIN A1 IN GATE_T__3_N_2;
 END;
 SYM INV GATE_T__3_I_2;
   PIN ZN0 OUT GATE_T__3_N_2;
   PIN A0 IN T__69;
 END;
 SYM INV GATE_T__3_I_1;
   PIN ZN0 OUT GATE_T__3_N_1;