ctl_1.abt

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MODULE ctl_1

" TOOL:     ispDesignEXPERT
" DATE:     Tue Apr 18 19:13:36 2006 
" TITLE:    hard-wired control unit
" MODULE:   ctl_1
" DESIGN:   ctl_1
" FILENAME: CTL_1.abt
" PROJECT:  untitled
" VERSION:  8.1

" NOTE: DO NOT EDIT THIS FILE DIRECTLY.
" This file is auto generated by ispDesignEXPERT System.
" It can be removed or overwritten automatically.
" If you want to edit this file, copy it to another file or 
" rename it with different file extension first. 


" Inputs
    W4 pin;
    W3 pin;
    W2 pin;
    W1 pin;
    T1 pin;
    SWC pin;
    SWB pin;
    SWA pin;
    PC_INC pin;
    MF pin;
    M2 pin;
    M1 pin;
    LDR4 pin;
    LDDR2 pin;
    LDAR1 pin;
    IR7 pin;
    IR6 pin;
    IR5 pin;
    IR4 pin;
    CLR pin;
    CER pin;
    C pin;


" Outputs
    WRD pin;
    TJ pin;
    SW_BUS pin;
    SKIP pin;
    S2 pin;
    S1 pin;
    S0 pin;
    RS_BUS pin;
    PC_ADD pin;
    M4 pin;
    M3 pin;
    LRW pin;
    LDPC pin;
    LDIR pin;
    LDER pin;
    LDDR1 pin;
    LDAR2 pin;
    CEL pin;
    AR1_INC pin;
    ALU_BUS pin;


" Bidirs



Test_vectors
([W4,W3,W2,W1,T1,SWC,SWB,SWA,PC_INC,MF,M2,M1,LDR4,LDDR2,LDAR1,IR7,IR6,IR5,IR4,CLR,CER,C] -> [WRD,TJ,SW_BUS,SKIP,S2,S1,S0,RS_BUS,PC_ADD,M4,M3,LRW,LDPC,LDIR,LDER,LDDR1,LDAR2,CEL,AR1_INC,ALU_BUS])


END