📄 ctl_1.tfi
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// TOOL: ispDesignEXPERT
// DATE: Tue Apr 18 19:24:36 2006
// TITLE: hard-wired control unit
// MODULE: ctl_1
// DESIGN: ctl_1
// FILENAME: CTL_1.tfi
// PROJECT: untitled
// VERSION: 8.1
// NOTE: DO NOT EDIT THIS FILE
// This file is auto generated by the ispDesignExpert System
// Inputs
reg W4;
reg W3;
reg W2;
reg W1;
reg T1;
reg SWC;
reg SWB;
reg SWA;
reg MF;
reg IR7;
reg IR6;
reg IR5;
reg IR4;
reg CLR;
reg C;
`ifdef has_xreset
`ifdef post_route
reg XRESET;
`endif
`endif
// Outputs
wire WRD;
wire TJ;
wire SW_BUS;
wire SKIP;
wire S2;
wire S1;
wire S0;
wire RS_BUS;
wire PC_ADD;
wire M4;
wire M3;
wire LRW;
wire LDPC;
wire LDIR;
wire LDER;
wire LDDR1;
wire LDAR1;
wire CEL;
wire AR1_INC;
wire ALU_BUS;
// Bidirs
// Instantiate the UUT
ctl_1 UUT (
`ifdef has_xreset
`ifdef post_route
.XRESET(XRESET),
`endif
`endif
.WRD(WRD),
.W4(W4),
.W3(W3),
.W2(W2),
.W1(W1),
.TJ(TJ),
.T1(T1),
.SW_BUS(SW_BUS),
.SWC(SWC),
.SWB(SWB),
.SWA(SWA),
.SKIP(SKIP),
.S2(S2),
.S1(S1),
.S0(S0),
.RS_BUS(RS_BUS),
.PC_ADD(PC_ADD),
.MF(MF),
.M4(M4),
.M3(M3),
.LRW(LRW),
.LDPC(LDPC),
.LDIR(LDIR),
.LDER(LDER),
.LDDR1(LDDR1),
.LDAR1(LDAR1),
.IR7(IR7),
.IR6(IR6),
.IR5(IR5),
.IR4(IR4),
.CLR(CLR),
.CEL(CEL),
.C(C),
.AR1_INC(AR1_INC),
.ALU_BUS(ALU_BUS)
);
// Initialize Inputs
`ifdef auto_init
initial begin
W4 = 0;
W3 = 0;
W2 = 0;
W1 = 0;
T1 = 0;
SWC = 0;
SWB = 0;
SWA = 0;
MF = 0;
IR7 = 0;
IR6 = 0;
IR5 = 0;
IR4 = 0;
CLR = 0;
C = 0;
end
`endif
`ifdef has_xreset
`ifdef post_route
initial begin
XRESET = 0;
#100 XRESET = 1;
end
`endif
`endif
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