ybx.abl

来自「上载硬部线学校课程设计」· ABL 代码 · 共 87 行

MODULE CTL_1

TITLE 'hard-wired control unit'
"INPUT 
CLR PIN 3;
MF,T1,W1,W2,W3,W4 PIN 5..10;
IR4,IR5,IR6,IR7 PIN 12..15;
SWC,SWB,SWA,C PIN 26..29;

"OUTPUT
MF1,SSTO NODE ISTYPE 'COM';
RUN,STO NODE ISTYPE 'REG';
LDIR,LDPC,PC_ADD,M4 PIN 30..33 ISTYPE 'COM';
LDAR1,AR1_INC,M3,CEL,LRW PIN 35..39 ISTYPE 'COM';
LDER,SW_BUS,RS_BUS,WRD PIN 45..48 ISTYPE 'COM';
LDDR1,S2,S1,S0,ALU_BUS PIN 52..56 ISTYPE 'COM';
TJ,SKIP PIN 69,70 ISTYPE 'COM';
CLK=.C.;
tKRR,tKRD,tKWE,tKLD,tPR NODE ISTYPE 'COM';
KRR1,KRD1,KWE1,KLD1,PR1,KRR2,KRD2,KWE2,KLD2,PR2 NODE ISTYPE 'COM';
ADD,SUB,MUL,AND,LDA,STA,JMP,JC,STP NODE ISTYPE 'COM';

EQUATIONS
MF1=!CLR&MF#T1;
RUN:=CLR&!STO#CLR&RUN;
RUN.CLK=MF1;
SSTO=!STO&RUN&W4;
STO:=CLR&SSTO#CLR&STO;
STO.CLK=MF1;


"指令译码部分
tKRR=SWC&!SWB&!SWA;
tKRD=!SWC&!SWB&SWA;
tKWE=!SWC&SWB&!SWA;
tKLD=!SWC&SWB&SWA;
 tPR=!SWC&!SWB&!SWA;
KRR1=!STO&tKRR;
KRR2=STO&tKRR;
KRD1=!STO&tKRD;
KRD2=STO&tKRD;
KWE1=!STO&tKWE;
KWE2=STO&tKWE;
KLD1=!STO&tKLD;
KLD2=STO&tKLD;
PR1=!STO&tPR;
PR2=STO&tPR;
ADD=PR2&(!IR7)&(!IR6)&(!IR5)&(!IR4);
SUB=PR2&(!IR7)&(!IR6)&(!IR5)&(IR4);
MUL=PR2&(!IR7)&(!IR6)&(IR5)&(!IR4);
AND=PR2&(!IR7)&(!IR6)&(IR5)&(IR4);
LDA=PR2&(!IR7)&(IR6)&(!IR5)&(IR4);
STA=PR2&(!IR7)&(IR6)&(!IR5)&(!IR4);
JMP=PR2&(IR7)&(!IR6)&(!IR5)&(!IR4);
JC=PR2&(IR7)&(!IR6)&(!IR5)&(IR4);
STP=PR2&(!IR7)&(IR6)&(IR5)&(!IR4);

"输出管脚
ALU_BUS=(ADD#SUB#MUL#AND)&W3#(STA&W4);
AR1_INC=(KRD2#KWE2)&W4;
CEL=!((KRD2#KWE2#KLD2#KRR2)&W1#(W3&LDA)#(W4&STA));
LDAR1=W4&(KRR1#KRD1#KWE1#KLD1)#(W2&LDA)#(W2&STA)#(PR2&W1);
"LDAR2=W4&(KRR1#KLD1)#(PR2&W1);
LDDR1=W2&(ADD#SUB#MUL#AND#STA);
"LDDR2=LDDR1#(W2&STA);
LDER=W3&(KLD2#ADD#SUB#MUL#AND#LDA);
LDPC=(W4&(PR1#JMP#(JC&C)));
"LDR4=LDPC;
LRW=W1&KRD2#W3&LDA;
"M1=!LDDR1;
"M2=!LDDR2;
M3=W4&(KRR1#KLD1);
M4=W4&(PR1#JMP);
LDIR=(W1&PR2)#((KLD2#KRR2)&W2#(W1&PR2));
PC_ADD=W4&JC&C;
RS_BUS=!(W2&(LDA#STA)#W4&(KRR2#JMP));
SW_BUS=!(W1&(KWE2#KLD2#KRR2)#(W3&KLD2)#(W4&!STO));
S0=SUB#STA;
S1=ADD#SUB;
S2=MUL;
SKIP=W1&!STO#(W1&(KRD2#KWE2))#(W2&(KRR2#STA))#W2&(JMP#JC#STP);
TJ=W1&KRD2#W2&KLD2#W4&(tKRR#tKWE#tKLD)#W4&STP;
WRD=W4&(KLD2#ADD#SUB#MUL#AND#LDA);

END