ctl_1.bl1

上载硬部线学校课程设计

#$ TOOL ispDesignEXPERT 8.1
#$ DATE Tue Apr 18 19:24:36 2006
#$ TITLE hard-wired control unit
#$ MODULE ctl_1
#$ JEDECFILE ctl_1
#$ PINS 35 CLR:3 MF:5 T1:6 W1:7 W2:8 W3:9 W4:10 IR4:12 IR5:13 IR6:14 IR7:15 SWC:26 SWB:27 SWA:28 C:29 LDIR:30 LDPC:31 PC_ADD:32 M4:33 LDAR1:35 AR1_INC:36 M3:37 \
#  CEL:38 LRW:39 LDER:45 SW_BUS:46 RS_BUS:47 WRD:48 LDDR1:52 S2:53 S1:54 S0:55 ALU_BUS:56 TJ:69 SKIP:70
#$ NODES 28 MF1 SSTO RUN STO tKRR tKRD tKWE tKLD tPR KRR1 KRD1 KWE1 KLD1 PR1 KRR2 KRD2 KWE2 KLD2 PR2 ADD SUB MUL AND LDA STA JMP JC STP

.model ctl_1
.inputs CLR.BLIF MF.BLIF T1.BLIF STO.BLIF RUN.BLIF MF1.BLIF W4.BLIF SSTO.BLIF \
SWC.BLIF SWB.BLIF SWA.BLIF tKRR.BLIF tKRD.BLIF tKWE.BLIF tKLD.BLIF tPR.BLIF \
PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF ADD.BLIF SUB.BLIF MUL.BLIF \
AND.BLIF W3.BLIF STA.BLIF KRD2.BLIF KWE2.BLIF KLD2.BLIF KRR2.BLIF W1.BLIF \
LDA.BLIF KRR1.BLIF KRD1.BLIF KWE1.BLIF KLD1.BLIF W2.BLIF PR1.BLIF JMP.BLIF \
JC.BLIF C.BLIF STP.BLIF
.outputs MF1 SSTO LDIR LDPC PC_ADD M4 LDAR1 AR1_INC M3 CEL LRW LDER SW_BUS \
RS_BUS WRD LDDR1 S2 S1 S0 ALU_BUS TJ SKIP tKRR tKRD tKWE tKLD tPR KRR1 KRD1 \
KWE1 KLD1 PR1 KRR2 KRD2 KWE2 KLD2 PR2 ADD SUB MUL AND LDA STA JMP JC STP \
RUN.REG RUN.C STO.REG STO.C
.names CLR.BLIF MF.BLIF T1.BLIF MF1
01- 1
--1 1
-00 0
1-0 0
.names STO.BLIF RUN.BLIF W4.BLIF SSTO
011 1
-0- 0
1-- 0
--0 0
.names PR2.BLIF KLD2.BLIF KRR2.BLIF W1.BLIF W2.BLIF LDIR
1--1- 1
--1-1 1
-1--1 1
-000- 0
000-- 0
---00 0
0---0 0
.names W4.BLIF PR1.BLIF JMP.BLIF JC.BLIF C.BLIF LDPC
1-1-- 1
11--- 1
1--11 1
-000- 0
-00-0 0
0---- 0
.names W4.BLIF JC.BLIF C.BLIF PC_ADD
111 1
-0- 0
0-- 0
--0 0
.names W4.BLIF PR1.BLIF JMP.BLIF M4
11- 1
1-1 1
-00 0
0-- 0
.names W4.BLIF PR2.BLIF STA.BLIF W1.BLIF LDA.BLIF KRR1.BLIF KRD1.BLIF \
KWE1.BLIF KLD1.BLIF W2.BLIF LDAR1
-1-1------ 1
1-------1- 1
1------1-- 1
1-----1--- 1
1----1---- 1
----1----1 1
--1------1 1
--0000000- 0
-00-00000- 0
---0-00000 0
-0---00000 0
0-000----- 0
000-0----- 0
0--0-----0 0
00-------0 0
.names W4.BLIF KRD2.BLIF KWE2.BLIF AR1_INC
11- 1
1-1 1
-00 0
0-- 0
.names W4.BLIF KRR1.BLIF KLD1.BLIF M3
11- 1
1-1 1
-00 0
0-- 0
.names W4.BLIF W3.BLIF STA.BLIF KRD2.BLIF KWE2.BLIF KLD2.BLIF KRR2.BLIF \
W1.BLIF LDA.BLIF CEL
-000000-- 1
00-0000-- 1
--00000-0 1
0--0000-0 1
-00----0- 1
00-----0- 1
--0----00 1
0------00 1
1-1------ 0
------11- 0
-----1-1- 0
----1--1- 0
---1---1- 0
-1------1 0
.names W3.BLIF KRD2.BLIF W1.BLIF LDA.BLIF LRW
-11- 1
1--1 1
0-0- 0
00-- 0
--00 0
-0-0 0
.names ADD.BLIF SUB.BLIF MUL.BLIF AND.BLIF W3.BLIF KLD2.BLIF LDA.BLIF LDER
----11- 1
---11-- 1
--1-1-- 1
-1--1-- 1
1---1-- 1
----1-1 1
0000-00 0
----0-- 0
.names STO.BLIF W4.BLIF W3.BLIF KWE2.BLIF KLD2.BLIF KRR2.BLIF W1.BLIF SW_BUS
-0-000- 1
1--000- 1
-00---0 1
1-0---0 1
-0--0-0 1
1---0-0 1
--1-1-- 0
01----- 0
-----11 0
---1--1 0
----1-1 0
.names W4.BLIF STA.BLIF KRR2.BLIF LDA.BLIF W2.BLIF JMP.BLIF RS_BUS
-000-0 1
00-0-- 1
--0-00 1
0---0- 1
1-1--- 0
---11- 0
-1--1- 0
1----1 0
.names W4.BLIF ADD.BLIF SUB.BLIF MUL.BLIF AND.BLIF KLD2.BLIF LDA.BLIF WRD
1----1- 1
1---1-- 1
1--1--- 1
1-1---- 1
11----- 1
1-----1 1
-000000 0
0------ 0
.names ADD.BLIF SUB.BLIF MUL.BLIF AND.BLIF STA.BLIF W2.BLIF LDDR1
----11 1
---1-1 1
--1--1 1
-1---1 1
1----1 1
00000- 0
-----0 0
.names ADD.BLIF SUB.BLIF S1
1- 1
-1 1
00 0
.names SUB.BLIF STA.BLIF S0
1- 1
-1 1
00 0
.names W4.BLIF ADD.BLIF SUB.BLIF MUL.BLIF AND.BLIF W3.BLIF STA.BLIF ALU_BUS
----11- 1
---1-1- 1
--1--1- 1
-1---1- 1
1-----1 1
00000-- 0
-0000-0 0
0----0- 0
-----00 0
.names W4.BLIF tKRR.BLIF tKWE.BLIF tKLD.BLIF KRD2.BLIF KLD2.BLIF W1.BLIF \
W2.BLIF STP.BLIF TJ
-----1-1- 1
----1-1-- 1
1--1----- 1
1-1------ 1
11------- 1
1-------1 1
-000--000 0
-0000--00 0
-000-00-0 0
-00000--0 0
0-----00- 0
0---0--0- 0
0----00-- 0
0---00--- 0
.names STO.BLIF STA.BLIF KRD2.BLIF KWE2.BLIF KRR2.BLIF W1.BLIF W2.BLIF \
JMP.BLIF JC.BLIF STP.BLIF SKIP
---1-1---- 1
--1--1---- 1
0----1---- 1
------1-1- 1
------11-- 1
----1-1--- 1
-1----1--- 1
------1--1 1
10000--000 0
-0--00-000 0
1-00--0--- 0
-----00--- 0
.names SWC.BLIF SWB.BLIF SWA.BLIF tKRR
100 1
-1- 0
0-- 0
--1 0
.names SWC.BLIF SWB.BLIF SWA.BLIF tKRD
001 1
-1- 0
1-- 0
--0 0
.names SWC.BLIF SWB.BLIF SWA.BLIF tKWE
010 1
-0- 0
1-- 0
--1 0
.names SWC.BLIF SWB.BLIF SWA.BLIF tKLD
011 1
-0- 0
1-- 0
--0 0
.names SWC.BLIF SWB.BLIF SWA.BLIF tPR
000 1
-1- 0
1-- 0
--1 0
.names STO.BLIF tKRR.BLIF KRR1
01 1
1- 0
-0 0
.names STO.BLIF tKRD.BLIF KRD1
01 1
1- 0
-0 0
.names STO.BLIF tKWE.BLIF KWE1
01 1
1- 0
-0 0
.names STO.BLIF tKLD.BLIF KLD1
01 1
1- 0
-0 0
.names STO.BLIF tPR.BLIF PR1
01 1
1- 0
-0 0
.names STO.BLIF tKRR.BLIF KRR2
11 1
0- 0
-0 0
.names STO.BLIF tKRD.BLIF KRD2
11 1
0- 0
-0 0
.names STO.BLIF tKWE.BLIF KWE2
11 1
0- 0
-0 0
.names STO.BLIF tKLD.BLIF KLD2
11 1
0- 0
-0 0
.names STO.BLIF tPR.BLIF PR2
11 1
0- 0
-0 0
.names PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF ADD
10000 1
---1- 0
--1-- 0
-1--- 0
0---- 0
----1 0
.names PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF SUB
10001 1
---1- 0
--1-- 0
-1--- 0
0---- 0
----0 0
.names PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF MUL
10010 1
---0- 0
--1-- 0
-1--- 0
0---- 0
----1 0
.names PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF AND
10011 1
---0- 0
--1-- 0
-1--- 0
0---- 0
----0 0
.names PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF LDA
10101 1
---1- 0
--0-- 0
-1--- 0
0---- 0
----0 0
.names PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF STA
10100 1
---1- 0
--0-- 0
-1--- 0
0---- 0
----1 0
.names PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF JMP
11000 1
---1- 0
--1-- 0
-0--- 0
0---- 0
----1 0
.names PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF JC
11001 1
---1- 0
--1-- 0
-0--- 0
0---- 0
----0 0
.names PR2.BLIF IR7.BLIF IR6.BLIF IR5.BLIF IR4.BLIF STP
10110 1
---0- 0
--0-- 0
-1--- 0
0---- 0
----1 0
.names CLR.BLIF STO.BLIF RUN.BLIF RUN.REG
10- 1
1-1 1
-10 0
0-- 0
.names CLR.BLIF STO.BLIF SSTO.BLIF STO.REG
11- 1
1-1 1
-00 0
0-- 0
.names MUL.BLIF S2
1 1
0 0
.names MF1.BLIF RUN.C
1 1
0 0
.names MF1.BLIF STO.C
1 1
0 0
.end