ctl_1.lst

上载硬部线学校课程设计

0002 |
0003 |TITLE 'hard-wired control unit'
0004 |"INPUT 
0005 |CLR PIN 3;
0006 |MF,T1,W1,W2,W3,W4 PIN 5..10;
0007 |IR4,IR5,IR6,IR7 PIN 12..15;
0008 |SWC,SWB,SWA,C PIN 26..29;
0009 |
0010 |"OUTPUT
0011 |MF1,SSTO NODE ISTYPE 'COM';
0012 |RUN,STO NODE ISTYPE 'REG';
0013 |LDIR,LDPC,PC_ADD,M4 PIN 30..33 ISTYPE 'COM';
0014 |LDAR1,AR1_INC,M3,CEL,LRW PIN 35..39 ISTYPE 'COM';
0015 |LDER,SW_BUS,RS_BUS,WRD PIN 45..48 ISTYPE 'COM';
0016 |LDDR1,S2,S1,S0,ALU_BUS PIN 52..56 ISTYPE 'COM';
0017 |TJ,SKIP PIN 69,70 ISTYPE 'COM';
0018 |CLK=.C.;
0019 |tKRR,tKRD,tKWE,tKLD,tPR NODE ISTYPE 'COM';
0020 |KRR1,KRD1,KWE1,KLD1,PR1,KRR2,KRD2,KWE2,KLD2,PR2 NODE ISTYPE 'COM';
0021 |ADD,SUB,MUL,AND,LDA,STA,JMP,JC,STP NODE ISTYPE 'COM';
0022 |
0023 |EQUATIONS
0024 |MF1=!CLR&MF#T1;
0025 |RUN:=CLR&!STO#CLR&RUN;
0026 |RUN.CLK=MF1;
0027 |SSTO=!STO&RUN&W4;
0028 |STO:=CLR&SSTO#CLR&STO;
0029 |STO.CLK=MF1;
0030 |
0031 |
0032 |"指令译码部分
0033 |tKRR=SWC&!SWB&!SWA;
0034 |tKRD=!SWC&!SWB&SWA;
0035 |tKWE=!SWC&SWB&!SWA;
0036 |tKLD=!SWC&SWB&SWA;
0037 | tPR=!SWC&!SWB&!SWA;
0038 |KRR1=!STO&tKRR;
0039 |KRR2=STO&tKRR;
0040 |KRD1=!STO&tKRD;
0041 |KRD2=STO&tKRD;
0042 |KWE1=!STO&tKWE;
0043 |KWE2=STO&tKWE;
0044 |KLD1=!STO&tKLD;
0045 |KLD2=STO&tKLD;
0046 |PR1=!STO&tPR;
0047 |PR2=STO&tPR;
0048 |ADD=PR2&(!IR7)&(!IR6)&(!IR5)&(!IR4);
0049 |SUB=PR2&(!IR7)&(!IR6)&(!IR5)&(IR4);
0050 |MUL=PR2&(!IR7)&(!IR6)&(IR5)&(!IR4);
0051 |AND=PR2&(!IR7)&(!IR6)&(IR5)&(IR4);
0052 |LDA=PR2&(!IR7)&(IR6)&(!IR5)&(IR4);
0053 |STA=PR2&(!IR7)&(IR6)&(!IR5)&(!IR4);
0054 |JMP=PR2&(IR7)&(!IR6)&(!IR5)&(!IR4);
0055 |JC=PR2&(IR7)&(!IR6)&(!IR5)&(IR4);
0056 |STP=PR2&(!IR7)&(IR6)&(IR5)&(!IR4);
0057 |
0058 |"输出管脚
0059 |ALU_BUS=(ADD#SUB#MUL#AND)&W3#(STA&W4);
0060 |AR1_INC=(KRD2#KWE2)&W4;
0061 |CEL=!((KRD2#KWE2#KLD2#KRR2)&W1#(W3&LDA)#(W4&STA));
0062 |LDAR1=W4&(KRR1#KRD1#KWE1#KLD1)#(W2&LDA)#(W2&STA)#(PR2&W1);
0063 |"LDAR2=W4&(KRR1#KLD1)#(PR2&W1);
0064 |LDDR1=W2&(ADD#SUB#MUL#AND#STA);
0065 |"LDDR2=LDDR1#(W2&STA);
0066 |LDER=W3&(KLD2#ADD#SUB#MUL#AND#LDA);
0067 |LDPC=(W4&(PR1#JMP#(JC&C)));
0068 |"LDR4=LDPC;
0069 |LRW=W1&KRD2#W3&LDA;
0070 |"M1=!LDDR1;
0071 |"M2=!LDDR2;
0072 |M3=W4&(KRR1#KLD1);
0073 |M4=W4&(PR1#JMP);
0074 |LDIR=(W1&PR2)#((KLD2#KRR2)&W2#(W1&PR2));
0075 |PC_ADD=W4&JC&C;
0076 |RS_BUS=!(W2&(LDA#STA)#W4&(KRR2#JMP));
0077 |SW_BUS=!(W1&(KWE2#KLD2#KRR2)#(W3&KLD2)#(W4&!STO));
0078 |S0=SUB#STA;
0079 |S1=ADD#SUB;
0080 |S2=MUL;
0081 |SKIP=W1&!STO#(W1&(KRD2#KWE2))#(W2&(KRR2#STA))#W2&(JMP#JC#STP);
0082 |TJ=W1&KRD2#W2&KLD2#W4&(tKRR#tKWE#tKLD)#W4&STP;
0083 |WRD=W4&(KLD2#ADD#SUB#MUL#AND#LDA);
0084 |
0085 |END
0086 |