untitled.tco

上载硬部线学校课程设计

Tco Path Report:
-----------------

Design Name: UNTITLED
Part Name: ispLSI1032E-100LJ84
   This report lists all the path delays from a primary input
   that drives the Clock input of a register, whose Q output
   drives a primary output

 Tco Path Definition:
 Tco =  Maximum delay from primary input to register clock_pin 
      + Maximum delay of register  clock-to-Q
      + Maximum delay from register Q_output to primary output


Tco Paths:

  Register            Source              Destination              Path Delay
  Name                Reference Clock     Primary Output             [ns]
==----------------------------------------------------------------------------------
  GLB_...BLIF *1      CLR                 LDDR1                    23.40 
  GLB_...BLIF *1      CLR                 LDIR                     23.40 
  GLB_...BLIF *1      CLR                 S0                       23.40 
  GLB_...BLIF *1      CLR                 RS_BUS                   23.40 
  GLB_...BLIF *1      CLR                 TJ                       25.20 
  GLB_...BLIF *1      CLR                 LRW                      23.40 
  GLB_...BLIF *1      CLR                 WRD                      23.40 
  GLB_...BLIF *1      CLR                 ALU_BUS                  23.40 
  GLB_...BLIF *1      CLR                 LDER                     23.40 
  GLB_...BLIF *1      CLR                 PC_ADD                   24.00 
  GLB_...BLIF *1      CLR                 SKIP                     23.60 
  GLB_...BLIF *1      CLR                 SW_BUS                   23.70 
  GLB_...BLIF *1      CLR                 M4                       23.40 
  GLB_...BLIF *1      CLR                 LDAR1                    25.20 
  GLB_...BLIF *1      CLR                 M3                       23.40 
  GLB_...BLIF *1      CLR                 LDPC                     23.40 
  GLB_...BLIF *1      CLR                 AR1_INC                  23.40 
  GLB_...BLIF *1      CLR                 S2                       24.00 
  GLB_...BLIF *1      CLR                 CEL                      25.20 
  GLB_...BLIF *1      CLR                 S1                       24.00 
  GLB_...BLIF *1      MF                  LDDR1                    23.40 
  GLB_...BLIF *1      MF                  LDIR                     23.40 
  GLB_...BLIF *1      MF                  S0                       23.40 
  GLB_...BLIF *1      MF                  RS_BUS                   23.40 
  GLB_...BLIF *1      MF                  TJ                       25.20 
  GLB_...BLIF *1      MF                  LRW                      23.40 
  GLB_...BLIF *1      MF                  WRD                      23.40 
  GLB_...BLIF *1      MF                  ALU_BUS                  23.40 
  GLB_...BLIF *1      MF                  LDER                     23.40 
  GLB_...BLIF *1      MF                  PC_ADD                   24.00 
  GLB_...BLIF *1      MF                  SKIP                     23.60 
  GLB_...BLIF *1      MF                  SW_BUS                   23.70 
  GLB_...BLIF *1      MF                  M4                       23.40 
  GLB_...BLIF *1      MF                  LDAR1                    25.20 
  GLB_...BLIF *1      MF                  M3                       23.40 
  GLB_...BLIF *1      MF                  LDPC                     23.40 
  GLB_...BLIF *1      MF                  AR1_INC                  23.40 
  GLB_...BLIF *1      MF                  S2                       24.00 
  GLB_...BLIF *1      MF                  CEL                      25.20 
  GLB_...BLIF *1      MF                  S1                       24.00 
  GLB_...BLIF *1      T1                  LDDR1                    23.40 
  GLB_...BLIF *1      T1                  LDIR                     23.40 
  GLB_...BLIF *1      T1                  S0                       23.40 
  GLB_...BLIF *1      T1                  RS_BUS                   23.40 
  GLB_...BLIF *1      T1                  TJ                       25.20 
  GLB_...BLIF *1      T1                  LRW                      23.40 
  GLB_...BLIF *1      T1                  WRD                      23.40 
  GLB_...BLIF *1      T1                  ALU_BUS                  23.40 
  GLB_...BLIF *1      T1                  LDER                     23.40 
  GLB_...BLIF *1      T1                  PC_ADD                   24.00 
  GLB_...BLIF *1      T1                  SKIP                     23.60 
  GLB_...BLIF *1      T1                  SW_BUS                   23.70 
  GLB_...BLIF *1      T1                  M4                       23.40 
  GLB_...BLIF *1      T1                  LDAR1                    25.20 
  GLB_...BLIF *1      T1                  M3                       23.40 
  GLB_...BLIF *1      T1                  LDPC                     23.40 
  GLB_...BLIF *1      T1                  AR1_INC                  23.40 
  GLB_...BLIF *1      T1                  S2                       24.00 
  GLB_...BLIF *1      T1                  CEL                      25.20 
  GLB_...BLIF *1      T1                  S1                       24.00 
==--------------------------------------------------------------------------------

Index Name Table
==----------------------------------------
    *1  GLB_STO_Q_BLIF
==----------------------------------------