ctl_1.eq0

上载硬部线学校课程设计

ispDesignEXPERT 8.1

Design ctl_1 created Tue Apr 18 19:24:36 2006

Title: hard-wired control unit

 P-Terms   Fan-in  Fan-out  Type  Name (attributes)
---------  ------  -------  ----  -----------------
   3          5        1    Pin   LDIR 
   3          5        1    Pin   LDPC 
   1          3        1    Pin   PC_ADD 
   2          3        1    Pin   M4 
   7         10        1    Pin   LDAR1 
   2          3        1    Pin   AR1_INC 
   2          3        1    Pin   M3 
   8          9        1    Pin   CEL 
   2          4        1    Pin   LRW 
   6          7        1    Pin   LDER 
   6          7        1    Pin   SW_BUS 
   4          6        1    Pin   RS_BUS 
   6          7        1    Pin   WRD 
   5          6        1    Pin   LDDR1 
   1/1        1        1    Pin   S2 
   2          2        1    Pin   S1 
   2          2        1    Pin   S0 
   5          7        1    Pin   ALU_BUS 
   6          9        1    Pin   TJ 
   8         10        1    Pin   SKIP 
   2          3        1    Node  MF1 
   1          3        1    Node  SSTO 
   2          3        1    Node  RUN.REG 
   1/1        1        1    Node  RUN.C 
   2          3        1    Node  STO.REG 
   1/1        1        1    Node  STO.C 
   1          3        1    Node  tKRR 
   1          3        1    Node  tKRD 
   1          3        1    Node  tKWE 
   1          3        1    Node  tKLD 
   1          3        1    Node  tPR 
   1          2        1    Node  KRR1 
   1          2        1    Node  KRD1 
   1          2        1    Node  KWE1 
   1          2        1    Node  KLD1 
   1          2        1    Node  PR1 
   1          2        1    Node  KRR2 
   1          2        1    Node  KRD2 
   1          2        1    Node  KWE2 
   1          2        1    Node  KLD2 
   1          2        1    Node  PR2 
   1          5        1    Node  ADD 
   1          5        1    Node  SUB 
   1          5        1    Node  MUL 
   1          5        1    Node  AND 
   1          5        1    Node  LDA 
   1          5        1    Node  STA 
   1          5        1    Node  JMP 
   1          5        1    Node  JC 
   1          5        1    Node  STP 
=========
 114/3          Best P-Term Total: 114
                       Total Pins: 35
                      Total Nodes: 28
            Average P-Term/Output: 2


Equations:

LDIR = (PR2 & W1
     # KRR2 & W2
     # KLD2 & W2);

LDPC = (W4 & JC & C
     # W4 & JMP
     # W4 & PR1);

PC_ADD = (W4 & JC & C);

M4 = (W4 & JMP
     # W4 & PR1);

LDAR1 = (PR2 & W1
     # LDA & W2
     # STA & W2
     # W4 & KLD1
     # W4 & KWE1
     # W4 & KRD1
     # W4 & KRR1);

AR1_INC = (W4 & KWE2
     # W4 & KRD2);

M3 = (W4 & KLD1
     # W4 & KRR1);

CEL = (!STA & !KRD2 & !KWE2 & !KLD2 & !KRR2 & !LDA
     # !W4 & !KRD2 & !KWE2 & !KLD2 & !KRR2 & !LDA
     # !W3 & !STA & !KRD2 & !KWE2 & !KLD2 & !KRR2
     # !W4 & !W3 & !KRD2 & !KWE2 & !KLD2 & !KRR2
     # !STA & !W1 & !LDA
     # !W4 & !W1 & !LDA
     # !W3 & !STA & !W1
     # !W4 & !W3 & !W1);

LRW = (W3 & LDA
     # KRD2 & W1);

LDER = (W3 & LDA
     # W3 & KLD2
     # AND & W3
     # MUL & W3
     # SUB & W3
     # ADD & W3);

SW_BUS = (!W4 & !KWE2 & !KLD2 & !KRR2
     # STO & !KWE2 & !KLD2 & !KRR2
     # !W4 & !W3 & !W1
     # STO & !W3 & !W1
     # !W4 & !KLD2 & !W1
     # STO & !KLD2 & !W1);

RS_BUS = (!STA & !KRR2 & !LDA & !JMP
     # !KRR2 & !W2 & !JMP
     # !W4 & !STA & !LDA
     # !W4 & !W2);

WRD = (W4 & LDA
     # W4 & KLD2
     # W4 & AND
     # W4 & MUL
     # W4 & SUB
     # W4 & ADD);

LDDR1 = (STA & W2
     # AND & W2
     # MUL & W2
     # SUB & W2
     # ADD & W2);

S2 = (MUL);

S1 = (SUB
     # ADD);

S0 = (STA
     # SUB);

ALU_BUS = (W4 & STA
     # AND & W3
     # MUL & W3
     # SUB & W3
     # ADD & W3);

TJ = (KLD2 & W2
     # KRD2 & W1
     # W4 & STP
     # W4 & tKLD
     # W4 & tKWE
     # W4 & tKRR);

SKIP = (KWE2 & W1
     # KRD2 & W1
     # !STO & W1
     # W2 & STP
     # W2 & JC
     # W2 & JMP
     # KRR2 & W2
     # STA & W2);

MF1 = (!CLR & MF
     # T1);

SSTO = (!STO & RUN & W4);

RUN := (CLR & RUN
     # CLR & !STO);

RUN.C = (MF1);

STO := (CLR & SSTO
     # CLR & STO);

STO.C = (MF1);

tKRR = (SWC & !SWB & !SWA);

tKRD = (!SWC & !SWB & SWA);

tKWE = (!SWC & SWB & !SWA);

tKLD = (!SWC & SWB & SWA);

tPR = (!SWC & !SWB & !SWA);

KRR1 = (!STO & tKRR);

KRD1 = (!STO & tKRD);

KWE1 = (!STO & tKWE);

KLD1 = (!STO & tKLD);

PR1 = (!STO & tPR);

KRR2 = (STO & tKRR);

KRD2 = (STO & tKRD);

KWE2 = (STO & tKWE);

KLD2 = (STO & tKLD);

PR2 = (STO & tPR);

ADD = (PR2 & !IR7 & !IR6 & !IR5 & !IR4);

SUB = (PR2 & !IR7 & !IR6 & !IR5 & IR4);

MUL = (PR2 & !IR7 & !IR6 & IR5 & !IR4);

AND = (PR2 & !IR7 & !IR6 & IR5 & IR4);

LDA = (PR2 & !IR7 & IR6 & !IR5 & IR4);

STA = (PR2 & !IR7 & IR6 & !IR5 & !IR4);

JMP = (PR2 & IR7 & !IR6 & !IR5 & !IR4);

JC = (PR2 & IR7 & !IR6 & !IR5 & IR4);

STP = (PR2 & !IR7 & IR6 & IR5 & !IR4);


Reverse-Polarity Equations:

!S2 = (!MUL);

!RUN.C = (!MF1);

!STO.C = (!MF1);