untitled.edf

上载硬部线学校课程设计

(edif ctl_1
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status (written
    (timeStamp 106 4 18 19 24 49)
    (program "blif2net" (version "ispDesignEXPERT 8.1"))))

  (external plsi
    (edifLevel 0)
    (technology (numberDefinition))

    (cell AND2
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port Z0 (direction OUTPUT))
        )
      )
    )

    (cell AND3
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port A2 (direction INPUT))
          (port Z0 (direction OUTPUT))
        )
      )
    )

    (cell AND4
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port A2 (direction INPUT))
          (port A3 (direction INPUT))
          (port Z0 (direction OUTPUT))
        )
      )
    )

    (cell INV
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port ZN0 (direction OUTPUT))
        )
      )
    )

    (cell NAND2
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port ZN0 (direction OUTPUT))
        )
      )
    )

    (cell NAND3
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port A2 (direction INPUT))
          (port ZN0 (direction OUTPUT))
        )
      )
    )

    (cell NAND4
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port A2 (direction INPUT))
          (port A3 (direction INPUT))
          (port ZN0 (direction OUTPUT))
        )
      )
    )

    (cell IB11
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port XI0 (direction INPUT))
          (port Z0 (direction OUTPUT))
        )
      )
    )

    (cell OB11
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port XO0 (direction OUTPUT))
        )
      )
    )

    (cell FD11
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port CLK (direction INPUT))
          (port D0 (direction INPUT))
          (port Q0 (direction OUTPUT))
        )
      )
    )
  )

  (library ctl_1
    (edifLevel 0)
    (technology (numberDefinition))

    (cell ctl_1
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port CLR (direction INPUT)
            (property LOCK (string "3"))
          )
          (port MF (direction INPUT)
            (property LOCK (string "5"))
          )
          (port T1 (direction INPUT)
            (property LOCK (string "6"))
          )
          (port W1 (direction INPUT)
            (property LOCK (string "7"))
          )
          (port W2 (direction INPUT)
            (property LOCK (string "8"))
          )
          (port W3 (direction INPUT)
            (property LOCK (string "9"))
          )
          (port W4 (direction INPUT)
            (property LOCK (string "10"))
          )
          (port IR4 (direction INPUT)
            (property LOCK (string "12"))
          )
          (port IR5 (direction INPUT)
            (property LOCK (string "13"))
          )
          (port IR6 (direction INPUT)
            (property LOCK (string "14"))
          )
          (port IR7 (direction INPUT)
            (property LOCK (string "15"))
          )
          (port SWC (direction INPUT)
            (property LOCK (string "26"))
          )
          (port SWB (direction INPUT)
            (property LOCK (string "27"))
          )
          (port SWA (direction INPUT)
            (property LOCK (string "28"))
          )
          (port C (direction INPUT)
            (property LOCK (string "29"))
          )
          (port LDIR (direction OUTPUT)
            (property LOCK (string "30"))
          )
          (port LDPC (direction OUTPUT)
            (property LOCK (string "31"))
          )
          (port PC_ADD (direction OUTPUT)
            (property LOCK (string "32"))
          )
          (port M4 (direction OUTPUT)
            (property LOCK (string "33"))
          )
          (port LDAR1 (direction OUTPUT)
            (property LOCK (string "35"))
          )
          (port AR1_INC (direction OUTPUT)
            (property LOCK (string "36"))
          )
          (port M3 (direction OUTPUT)
            (property LOCK (string "37"))
          )
          (port CEL (direction OUTPUT)
            (property LOCK (string "38"))
          )
          (port LRW (direction OUTPUT)
            (property LOCK (string "39"))
          )
          (port LDER (direction OUTPUT)
            (property LOCK (string "45"))
          )
          (port SW_BUS (direction OUTPUT)
            (property LOCK (string "46"))
          )
          (port RS_BUS (direction OUTPUT)
            (property LOCK (string "47"))
          )
          (port WRD (direction OUTPUT)
            (property LOCK (string "48"))
          )
          (port LDDR1 (direction OUTPUT)
            (property LOCK (string "52"))
          )
          (port S1 (direction OUTPUT)
            (property LOCK (string "54"))
          )
          (port S0 (direction OUTPUT)
            (property LOCK (string "55"))
          )
          (port ALU_BUS (direction OUTPUT)
            (property LOCK (string "56"))
          )
          (port TJ (direction OUTPUT)
            (property LOCK (string "69"))
          )
          (port SKIP (direction OUTPUT)
            (property LOCK (string "70"))
          )
          (port S2 (direction OUTPUT)
            (property LOCK (string "53"))
          )
        )

        (contents
          (instance IN_CLR_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_MF_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_T1_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_W1_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_W2_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_W3_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_W4_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_IR4_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_IR5_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_IR6_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_IR7_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_SWC_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_SWB_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance IN_SWA_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))