untitled.rpt

上载硬部线学校课程设计

        10 Input(s)
            W3X, SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, W4X, IR7X, SWBX,
            IR5X
        1 Fanout(s)
            ALU_BUS.IR
        2 Product Term(s)
        1 GLB Level(s)

        ALU_BUS_COM_BLIF = STO_Q_BLIF & W3X & !IR7X & !SWAX & !SWBX
            & !SWCX & !IR6X
            # STO_Q_BLIF & IR6X & W4X & !IR4X & !IR5X & !IR7X & !SWAX
            & !SWBX & !SWCX


Clock GLB glb06, C0

    15 Input(s)
        (CLR.O, CLRX, I15), (glb06.O3, RUN_Q_BLIF, I17), (glb06.O0, 
        STO_Q_BLIF, I16), (IR4.O, IR4X, I6), (IR5.O, IR5X, I14), 
        (IR6.O, IR6X, I4), (IR7.O, IR7X, I7), (MF.O, MFX, I13), (SWA.O, 
        SWAX, I9), (SWB.O, SWBX, I10), (SWC.O, SWCX, I11), (T1.O, 
        T1X, I12), (W1.O, W1X, I0), (W2.O, W2X, I1), (W4.O, W4X, I8)
    4 Output(s)
        (STO_Q_BLIF, O0), (STO_C, O1), (SKIP_COM_BLIF, O2), 
        (RUN_Q_BLIF, O3)
    12 Product Term(s)

    Output STO_Q_BLIF

        4 Input(s)
            STO_Q_BLIF, RUN_Q_BLIF, CLRX, W4X
        8 Fanout(s)
            glb00.I0, glb02.I0, glb01.I0, glb05.I0, glb03.I0, glb04.I0,
            glb06.I16, glb07.I15
        2 Product Term(s)
        1 GLB Level(s)

        STO_Q_BLIF.D = (CLRX & STO_Q_BLIF
            # CLRX & RUN_Q_BLIF & W4X)
        STO_Q_BLIF.C = STO_C
        STO_Q_BLIF.R = 
    Output STO_C

        3 Input(s)
            T1X, CLRX, MFX
        1 Fanout(s)
            glb06.CLK2
        2 Product Term(s)
        1 GLB Level(s)

        STO_C = (T1X
            # MFX & !CLRX)

    Output SKIP_COM_BLIF

        10 Input(s)
            SWAX, IR6X, STO_Q_BLIF, W2X, SWCX, IR4X, IR7X, W1X, SWBX,
            IR5X
        1 Fanout(s)
            SKIP.IR
        6 Product Term(s)
        1 GLB Level(s)

        SKIP_COM_BLIF = (W1X & !STO_Q_BLIF
            # SWBX & W1X & !SWAX & !SWCX
            # SWAX & W1X & !SWBX & !SWCX
            # STO_Q_BLIF & SWCX & W2X & !SWAX & !SWBX
            # STO_Q_BLIF & IR6X & W2X & !IR4X & !IR7X & !SWAX & !SWBX
            # STO_Q_BLIF & IR7X & W2X & !IR5X & !SWAX & !SWBX & !IR6X)

    Output RUN_Q_BLIF

        3 Input(s)
            STO_Q_BLIF, RUN_Q_BLIF, CLRX
        1 Fanout(s)
            glb06.I17
        2 Product Term(s)
        1 GLB Level(s)

        RUN_Q_BLIF.D = (CLRX & RUN_Q_BLIF
            # CLRX & !STO_Q_BLIF)
        RUN_Q_BLIF.C = STO_C
        RUN_Q_BLIF.R = 

GLB glb07, C1

    11 Input(s)
        (glb06.O0, STO_Q_BLIF, I15), (IR4.O, IR4X, I13), (IR5.O, 
        IR5X, I14), (IR6.O, IR6X, I4), (IR7.O, IR7X, I7), (SWA.O, 
        SWAX, I9), (SWB.O, SWBX, I10), (SWC.O, SWCX, I11), (W1.O, 
        W1X, I0), (W2.O, W2X, I1), (W4.O, W4X, I8)
    1 Output(s)
        (TJ_COM_BLIF, O1)
    5 Product Term(s)

    Output TJ_COM_BLIF

        11 Input(s)
            SWAX, IR6X, STO_Q_BLIF, W2X, SWCX, IR4X, W4X, IR7X, W1X,
            SWBX, IR5X
        1 Fanout(s)
            TJ.IR
        5 Product Term(s)
        1 GLB Level(s)

        TJ_COM_BLIF = (SWBX & W4X & !SWCX
            # SWCX & W4X & !SWAX & !SWBX
            # STO_Q_BLIF & SWAX & W1X & !SWBX & !SWCX
            # STO_Q_BLIF & SWAX & SWBX & W2X & !SWCX
            # STO_Q_BLIF & IR5X & IR6X & W4X & !IR4X & !IR7X & !SWAX
            & !SWCX)


Output ALU_BUS, IO27

    Input (glb05.O3, ALU_BUS_COM_BLIF)

    ALU_BUS = ALU_BUS_COM_BLIF


Output AR1_INC, IO10

    Input (glb02.O2, AR1_INC_COM_BLIF)

    AR1_INC = AR1_INC_COM_BLIF


Input C, IO3

    Output CX
        1 Fanout(s)
            glb01.I3


Output CEL, IO12

    Input (glb01.O0, OR_1011)

    CEL = !OR_1011


Input CLR, IO48

    Output CLRX
        1 Fanout(s)
            glb06.I15


Input IR4, IO57

    Output IR4X
        7 Fanout(s)
            glb00.I2, glb01.I2, glb05.I2, glb03.I2, glb04.I2, glb06.I6,
            glb07.I13


Input IR5, IO58

    Output IR5X
        8 Fanout(s)
            glb00.I1, glb02.I1, glb01.I1, glb05.I1, glb03.I1, glb04.I1,
            glb06.I14, glb07.I14


Input IR6, IO59

    Output IR6X
        8 Fanout(s)
            glb00.I11, glb02.I11, glb01.I11, glb05.I11, glb03.I11,
            glb04.I11, glb06.I4, glb07.I4


Input IR7, IO60

    Output IR7X
        8 Fanout(s)
            glb00.I8, glb02.I8, glb01.I8, glb05.I8, glb03.I8, glb04.I8,
            glb06.I7, glb07.I7


Output LDAR1, IO9

    Input (glb02.O1, LDAR1_COM_BLIF)

    LDAR1 = LDAR1_COM_BLIF


Output LDDR1, IO23

    Input (glb03.O3, OR_758)

    LDDR1 = OR_758


Output LDER, IO16

    Input (glb05.O0, LDER_COM_BLIF)

    LDER = LDER_COM_BLIF


Output LDIR, IO4

    Input (glb02.O0, LDIR_COM_BLIF)

    LDIR = LDIR_COM_BLIF


Output LDPC, IO5

    Input (glb01.O1, LDPC_COM_BLIF)

    LDPC = LDPC_COM_BLIF


Output LRW, IO13

    Input (glb00.O1, LRW_COM_BLIF)

    LRW = LRW_COM_BLIF


Output M3, IO11

    Input (glb02.O3, M3_COM_BLIF)

    M3 = M3_COM_BLIF


Output M4, IO7

    Input (glb01.O3, M4_COM_BLIF)

    M4 = M4_COM_BLIF


Input MF, IO50

    Output MFX
        1 Fanout(s)
            glb06.I13


Output PC_ADD, IO6

    Input (glb01.O2, PC_ADD_COM_BLIF)

    PC_ADD = PC_ADD_COM_BLIF


Output RS_BUS, IO18

    Input (glb04.O2, OR_1010)

    RS_BUS = !OR_1010


Output S0, IO26

    Input (glb05.O2, S0_COM_BLIF)

    S0 = S0_COM_BLIF


Output S1, IO25

    Input (glb04.O1, S1_COM_BLIF)

    S1 = S1_COM_BLIF


Output S2, IO24

    Input (glb04.O0, S2_COM_BLIF)

    S2 = S2_COM_BLIF


Output SKIP, IO34

    Input (glb06.O2, SKIP_COM_BLIF)

    SKIP = SKIP_COM_BLIF


Input SWA, IO2

    Output SWAX
        8 Fanout(s)
            glb00.I6, glb02.I2, glb01.I6, glb05.I6, glb03.I6, glb04.I6,
            glb06.I9, glb07.I9


Input SWB, IO1

    Output SWBX
        8 Fanout(s)
            glb00.I5, glb02.I5, glb01.I5, glb05.I5, glb03.I5, glb04.I5,
            glb06.I10, glb07.I10


Input SWC, IO0

    Output SWCX
        8 Fanout(s)
            glb00.I4, glb02.I4, glb01.I4, glb05.I4, glb03.I4, glb04.I4,
            glb06.I11, glb07.I11


Output SW_BUS, IO17

    Input (glb05.O1, OR_1012)

    SW_BUS = !OR_1012


Input T1, IO51

    Output T1X
        1 Fanout(s)
            glb06.I12


Output TJ, IO33

    Input (glb07.O1, TJ_COM_BLIF)

    TJ = TJ_COM_BLIF


Input W1, IO52

    Output W1X
        6 Fanout(s)
            glb00.I15, glb02.I15, glb01.I15, glb05.I15, glb06.I0,
            glb07.I0


Input W2, IO53

    Output W2X
        5 Fanout(s)
            glb02.I14, glb03.I14, glb04.I14, glb06.I1, glb07.I1


Input W3, IO54

    Output W3X
        3 Fanout(s)
            glb00.I13, glb01.I13, glb05.I13


Input W4, IO55

    Output W4X
        6 Fanout(s)
            glb02.I7, glb01.I7, glb05.I7, glb04.I7, glb06.I8, glb07.I8


Output WRD, IO19

    Input (glb04.O3, OR_734)

    WRD = OR_734


Clock Assignments

    Net Name		    Clock Assignment

        STO_C                   Internal CLK2


GLB and GLB Output Statistics

    GLB Name, Location      GLB Statistics          GLB Output Statistics
    GLB Output Name         Ins, Outs, PTs          Ins, FOs, PTs, Levels, PTSABP

        glb00, A2               10,  1,  2          
            LRW_COM_BLIF                                10,  1,  2,  1, 4PT 

        glb01, A6               12,  4, 11          
            LDPC_COM_BLIF                               10,  1,  3,  1, 4PT 
            M4_COM_BLIF                                  9,  1,  2,  1, 4PT 
            OR_1011                                     11,  1,  5,  1, -   
            PC_ADD_COM_BLIF                             10,  1,  1,  1, 1PT 

        glb02, A3               10,  4, 11          
            AR1_INC_COM_BLIF                             5,  1,  2,  1, 4PT 
            LDAR1_COM_BLIF                              10,  1,  4,  1, -   
            LDIR_COM_BLIF                                6,  1,  3,  1, 4PT 
            M3_COM_BLIF                                  5,  1,  2,  1, 4PT 

        glb03, B3                9,  1,  2          
            OR_758                                       9,  1,  2,  1, 4PT 

        glb04, B6               10,  4,  8          
            OR_1010                                     10,  1,  3,  1, 4PT 
            OR_734                                       9,  1,  3,  1, 4PT 
            S1_COM_BLIF                                  7,  1,  1,  1, 1PT 
            S2_COM_BLIF                                  8,  1,  1,  1, 1PT 

        glb05, B1               11,  4, 11          
            ALU_BUS_COM_BLIF                            10,  1,  2,  1, 4PT 
            LDER_COM_BLIF                                9,  1,  3,  1, 4PT 
            OR_1012                                      7,  1,  4,  1, 4PT 
            S0_COM_BLIF                                  8,  1,  2,  1, 4PT 

        glb06, C0               15,  4, 12          
            RUN_Q_BLIF                                   3,  1,  2,  1, -   
            SKIP_COM_BLIF                               10,  1,  6,  1, -   
            STO_C                                        3,  1,  2,  1, -   
            STO_Q_BLIF                                   4,  8,  2,  1, -   

        glb07, C1               11,  1,  5          
            TJ_COM_BLIF                                 11,  1,  5,  1, -   


Pin Assignments

    Pin Name                Pin Assignment          Pin Type, Pin Attribute

        CLR                     3                       Input, PULLUP
        MF                      5                       Input, PULLUP
        T1                      6                       Input, PULLUP
        W1                      7                       Input, PULLUP
        W2                      8                       Input, PULLUP
        W3                      9                       Input, PULLUP
        W4                      10                      Input, PULLUP
        IR4                     12                      Input, PULLUP
        IR5                     13                      Input, PULLUP
        IR6                     14                      Input, PULLUP
        IR7                     15                      Input, PULLUP
        SWC                     26                      Input, PULLUP
        SWB                     27                      Input, PULLUP
        SWA                     28                      Input, PULLUP
        C                       29                      Input, PULLUP
        LDIR                    30                      Output, PULLUP
        LDPC                    31                      Output, PULLUP
        PC_ADD                  32                      Output, PULLUP
        M4                      33                      Output, PULLUP
        LDAR1                   35                      Output, PULLUP
        AR1_INC                 36                      Output, PULLUP
        M3                      37                      Output, PULLUP
        CEL                     38                      Output, PULLUP
        LRW                     39                      Output, PULLUP
        LDER                    45                      Output, PULLUP
        SW_BUS                  46                      Output, PULLUP
        RS_BUS                  47                      Output, PULLUP
        WRD                     48                      Output, PULLUP
        LDDR1                   52                      Output, PULLUP
        S2                      53                      Output, PULLUP
        S1                      54                      Output, PULLUP
        S0                      55                      Output, PULLUP
        ALU_BUS                 56                      Output, PULLUP
        TJ                      69                      Output, PULLUP
        SKIP                    70                      Output, PULLUP


Design process management completed successfully