untitled.rpt

上载硬部线学校课程设计

ispEXPERT Compiler Release 8.1.19.32, Jun 28 2000 11:25:29


Design Parameters
-----------------

EFFORT:                         MEDIUM (2)
IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16
MAX_GLB_OUT:                    4
OS_VERSION:                     Windows NT 5.0
PARAM_FILE:                     _untitle
PIN_FILE:                       untitled.xpn
STRATEGY:                       DELAY
TIMING_ANALYZER:                FREQUENCY SETUP_HOLD CLOCK_TO_OUTPUT PRIMARY_IN_TO_OUT 
USE_GLOBAL_RESET:               ON
XOR:                            OFF


Design Specification
--------------------

Design:                         untitled
Part:                           ispLSI1032E-100LJ84


ISP:                            OFF
PULL:                           UP
SECURITY:                       OFF
SLOWSLEW:                       OFF


Number of Critical Pins:        0
Number of Free Pins:            0
Number of Locked Pins:          35
Number of Reserved Pins:        0


Input Pins

    Pin Name                Pin Attribute

        C                       LOCK 29, PULLUP
        CLR                     LOCK 3, PULLUP
        IR4                     LOCK 12, PULLUP
        IR5                     LOCK 13, PULLUP
        IR6                     LOCK 14, PULLUP
        IR7                     LOCK 15, PULLUP
        MF                      LOCK 5, PULLUP
        SWA                     LOCK 28, PULLUP
        SWB                     LOCK 27, PULLUP
        SWC                     LOCK 26, PULLUP
        T1                      LOCK 6, PULLUP
        W1                      LOCK 7, PULLUP
        W2                      LOCK 8, PULLUP
        W3                      LOCK 9, PULLUP
        W4                      LOCK 10, PULLUP


Output Pins

    Pin Name                Pin Attribute

        ALU_BUS                 LOCK 56, PULLUP
        AR1_INC                 LOCK 36, PULLUP
        CEL                     LOCK 38, PULLUP
        LDAR1                   LOCK 35, PULLUP
        LDDR1                   LOCK 52, PULLUP
        LDER                    LOCK 45, PULLUP
        LDIR                    LOCK 30, PULLUP
        LDPC                    LOCK 31, PULLUP
        LRW                     LOCK 39, PULLUP
        M3                      LOCK 37, PULLUP
        M4                      LOCK 33, PULLUP
        PC_ADD                  LOCK 32, PULLUP
        RS_BUS                  LOCK 47, PULLUP
        S0                      LOCK 55, PULLUP
        S1                      LOCK 54, PULLUP
        S2                      LOCK 53, PULLUP
        SKIP                    LOCK 70, PULLUP
        SW_BUS                  LOCK 46, PULLUP
        TJ                      LOCK 69, PULLUP
        WRD                     LOCK 48, PULLUP


Pre-Route Design Statistics
---------------------------

Number of Macrocells:           23
Number of GLBs:                 8
Number of I/Os:                 35
Number of Nets:                 37

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    15
Number of Locked DIs:           0
Number of Locked Outputs:       20
Number of Locked Three-States:  0
Number of Locked Bidi's:        0

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      0


GLB Utilization (Out of 32):	25%
I/O Utilization (Out of 72):	48%
Net Utilization (Out of 200):	18%


Nets with Fanout of  1:         25
Nets with Fanout of  3:         1
Nets with Fanout of  5:         1
Nets with Fanout of  6:         2
Nets with Fanout of  7:         1
Nets with Fanout of  8:         7

Average Fanout per Net:         2.92


GLBs with  9 Input(s):          1
GLBs with 10 Input(s):          3
GLBs with 11 Input(s):          2
GLBs with 12 Input(s):          1
GLBs with 15 Input(s):          1

Average Inputs per GLB:         11.00


GLBs with  1 Output(s):         3
GLBs with  4 Output(s):         5

Average Outputs per GLB:        2.88


Number of GLB Registers:        2
Number of IOC Registers:        0


Post-Route Design Implementation
--------------------------------

Number of Macrocells:		23
Number of GLBs:			8
Number of IOCs:			35
Number of DIs:			0
Number of GLB Levels:		1


GLB glb00, A2

    10 Input(s)
        (glb06.O0, STO_Q_BLIF, I0), (IR4.O, IR4X, I2), (IR5.O, 
        IR5X, I1), (IR6.O, IR6X, I11), (IR7.O, IR7X, I8), (SWA.O, 
        SWAX, I6), (SWB.O, SWBX, I5), (SWC.O, SWCX, I4), (W1.O, 
        W1X, I15), (W3.O, W3X, I13)
    1 Output(s)
        (LRW_COM_BLIF, O1)
    2 Product Term(s)

    Output LRW_COM_BLIF

        10 Input(s)
            W3X, SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, IR7X, W1X, SWBX,
            IR5X
        1 Fanout(s)
            LRW.IR
        2 Product Term(s)
        1 GLB Level(s)

        LRW_COM_BLIF = STO_Q_BLIF & SWAX & W1X & !SWBX & !SWCX
            # STO_Q_BLIF & IR4X & IR6X & W3X & !IR5X & !IR7X & !SWAX
            & !SWBX & !SWCX


GLB glb01, A6

    12 Input(s)
        (C.O, CX, I3), (glb06.O0, STO_Q_BLIF, I0), (IR4.O, IR4X, I2), 
        (IR5.O, IR5X, I1), (IR6.O, IR6X, I11), (IR7.O, IR7X, I8), 
        (SWA.O, SWAX, I6), (SWB.O, SWBX, I5), (SWC.O, SWCX, I4), (W1.O, 
        W1X, I15), (W3.O, W3X, I13), (W4.O, W4X, I7)
    4 Output(s)
        (PC_ADD_COM_BLIF, O2), (OR_1011, O0), (M4_COM_BLIF, O3), 
        (LDPC_COM_BLIF, O1)
    11 Product Term(s)

    Output PC_ADD_COM_BLIF

        10 Input(s)
            SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, W4X, IR7X, CX, SWBX,
            IR5X
        1 Fanout(s)
            PC_ADD.IR
        1 Product Term(s)
        1 GLB Level(s)

        PC_ADD_COM_BLIF = CX & STO_Q_BLIF & IR4X & IR7X & W4X & !IR5X
            & !SWAX & !SWBX & !SWCX & !IR6X

    Output OR_1011

        11 Input(s)
            W3X, SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, W4X, IR7X, W1X,
            SWBX, IR5X
        1 Fanout(s)
            CEL.IR
        5 Product Term(s)
        1 GLB Level(s)

        OR_1011 = (STO_Q_BLIF & SWAX & W1X & !SWCX
            # STO_Q_BLIF & SWBX & W1X & !SWCX
            # STO_Q_BLIF & SWCX & W1X & !SWAX & !SWBX
            # STO_Q_BLIF & IR4X & IR6X & W3X & !IR5X & !IR7X & !SWAX
            & !SWBX & !SWCX
            # STO_Q_BLIF & IR6X & W4X & !IR4X & !IR5X & !IR7X & !SWAX
            & !SWBX & !SWCX)

    Output M4_COM_BLIF

        9 Input(s)
            SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, W4X, IR7X, SWBX, IR5X
        1 Fanout(s)
            M4.IR
        2 Product Term(s)
        1 GLB Level(s)

        M4_COM_BLIF = W4X & !SWAX & !SWBX & !SWCX & !STO_Q_BLIF
            # IR7X & W4X & !IR4X & !IR5X & !SWAX & !SWBX & !SWCX & !IR6X

    Output LDPC_COM_BLIF

        10 Input(s)
            SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, W4X, IR7X, CX, SWBX,
            IR5X
        1 Fanout(s)
            LDPC.IR
        3 Product Term(s)
        1 GLB Level(s)

        LDPC_COM_BLIF = W4X & !SWAX & !SWBX & !SWCX & !STO_Q_BLIF
            # CX & IR7X & W4X & !IR5X & !SWAX & !SWBX & !SWCX & !IR6X
            # IR7X & W4X & !IR4X & !IR5X & !SWAX & !SWBX & !SWCX & !IR6X


GLB glb02, A3

    10 Input(s)
        (glb06.O0, STO_Q_BLIF, I0), (IR5.O, IR5X, I1), (IR6.O, 
        IR6X, I11), (IR7.O, IR7X, I8), (SWA.O, SWAX, I2), (SWB.O, 
        SWBX, I5), (SWC.O, SWCX, I4), (W1.O, W1X, I15), (W2.O, 
        W2X, I14), (W4.O, W4X, I7)
    4 Output(s)
        (M3_COM_BLIF, O3), (LDIR_COM_BLIF, O0), (LDAR1_COM_BLIF, O1), 
        (AR1_INC_COM_BLIF, O2)
    11 Product Term(s)

    Output M3_COM_BLIF

        5 Input(s)
            SWAX, STO_Q_BLIF, SWCX, W4X, SWBX
        1 Fanout(s)
            M3.IR
        2 Product Term(s)
        1 GLB Level(s)

        M3_COM_BLIF = SWCX & W4X & !SWAX & !SWBX & !STO_Q_BLIF
            # SWAX & SWBX & W4X & !SWCX & !STO_Q_BLIF

    Output LDIR_COM_BLIF

        6 Input(s)
            SWAX, STO_Q_BLIF, W2X, SWCX, W1X, SWBX
        1 Fanout(s)
            LDIR.IR
        3 Product Term(s)
        1 GLB Level(s)

        LDIR_COM_BLIF = STO_Q_BLIF & W1X & !SWAX & !SWBX & !SWCX
            # STO_Q_BLIF & SWCX & W2X & !SWAX & !SWBX
            # STO_Q_BLIF & SWAX & SWBX & W2X & !SWCX

    Output LDAR1_COM_BLIF

        10 Input(s)
            SWAX, IR6X, STO_Q_BLIF, W2X, SWCX, W4X, IR7X, W1X, SWBX,
            IR5X
        1 Fanout(s)
            LDAR1.IR
        4 Product Term(s)
        1 GLB Level(s)

        LDAR1_COM_BLIF = (W4X & !SWAX & !SWBX & !STO_Q_BLIF
            # STO_Q_BLIF & W1X & !SWAX & !SWBX & !SWCX
            # STO_Q_BLIF & IR6X & W2X & !IR5X & !IR7X & !SWAX & !SWBX
            & !SWCX)
            $ W4X & !SWCX & !STO_Q_BLIF

    Output AR1_INC_COM_BLIF

        5 Input(s)
            SWAX, STO_Q_BLIF, SWCX, W4X, SWBX
        1 Fanout(s)
            AR1_INC.IR
        2 Product Term(s)
        1 GLB Level(s)

        AR1_INC_COM_BLIF = STO_Q_BLIF & SWBX & W4X & !SWAX & !SWCX
            # STO_Q_BLIF & SWAX & W4X & !SWBX & !SWCX


GLB glb03, B3

    9 Input(s)
        (glb06.O0, STO_Q_BLIF, I0), (IR4.O, IR4X, I2), (IR5.O, 
        IR5X, I1), (IR6.O, IR6X, I11), (IR7.O, IR7X, I8), (SWA.O, 
        SWAX, I6), (SWB.O, SWBX, I5), (SWC.O, SWCX, I4), (W2.O, 
        W2X, I14)
    1 Output(s)
        (OR_758, O3)
    2 Product Term(s)

    Output OR_758

        9 Input(s)
            SWAX, IR6X, STO_Q_BLIF, W2X, SWCX, IR4X, IR7X, SWBX, IR5X
        1 Fanout(s)
            LDDR1.IR
        2 Product Term(s)
        1 GLB Level(s)

        OR_758 = STO_Q_BLIF & W2X & !IR7X & !SWAX & !SWBX & !SWCX & !IR6X
            # STO_Q_BLIF & W2X & !IR4X & !IR5X & !IR7X & !SWAX & !SWBX
            & !SWCX


GLB glb04, B6

    10 Input(s)
        (glb06.O0, STO_Q_BLIF, I0), (IR4.O, IR4X, I2), (IR5.O, 
        IR5X, I1), (IR6.O, IR6X, I11), (IR7.O, IR7X, I8), (SWA.O, 
        SWAX, I6), (SWB.O, SWBX, I5), (SWC.O, SWCX, I4), (W2.O, 
        W2X, I14), (W4.O, W4X, I7)
    4 Output(s)
        (S2_COM_BLIF, O0), (S1_COM_BLIF, O1), (OR_734, O3), 
        (OR_1010, O2)
    8 Product Term(s)

    Output S2_COM_BLIF

        8 Input(s)
            SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, IR7X, SWBX, IR5X
        1 Fanout(s)
            S2.IR
        1 Product Term(s)
        1 GLB Level(s)

        S2_COM_BLIF = STO_Q_BLIF & IR5X & !IR4X & !IR7X & !SWAX & !SWBX
            & !SWCX & !IR6X

    Output S1_COM_BLIF

        7 Input(s)
            SWAX, IR6X, STO_Q_BLIF, SWCX, IR7X, SWBX, IR5X
        1 Fanout(s)
            S1.IR
        1 Product Term(s)
        1 GLB Level(s)

        S1_COM_BLIF = STO_Q_BLIF & !IR5X & !IR7X & !SWAX & !SWBX & !SWCX
            & !IR6X

    Output OR_734

        9 Input(s)
            SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, W4X, IR7X, SWBX, IR5X
        1 Fanout(s)
            WRD.IR
        3 Product Term(s)
        1 GLB Level(s)

        OR_734 = STO_Q_BLIF & SWAX & SWBX & W4X & !SWCX
            # STO_Q_BLIF & W4X & !IR7X & !SWAX & !SWBX & !SWCX & !IR6X
            # STO_Q_BLIF & IR4X & W4X & !IR5X & !IR7X & !SWAX & !SWBX
            & !SWCX

    Output OR_1010

        10 Input(s)
            SWAX, IR6X, STO_Q_BLIF, W2X, SWCX, IR4X, W4X, IR7X, SWBX,
            IR5X
        1 Fanout(s)
            RS_BUS.IR
        3 Product Term(s)
        1 GLB Level(s)

        OR_1010 = STO_Q_BLIF & SWCX & W4X & !SWAX & !SWBX
            # STO_Q_BLIF & IR6X & W2X & !IR5X & !IR7X & !SWAX & !SWBX
            & !SWCX
            # STO_Q_BLIF & IR7X & W4X & !IR4X & !IR5X & !SWAX & !SWBX
            & !IR6X


GLB glb05, B1

    11 Input(s)
        (glb06.O0, STO_Q_BLIF, I0), (IR4.O, IR4X, I2), (IR5.O, 
        IR5X, I1), (IR6.O, IR6X, I11), (IR7.O, IR7X, I8), (SWA.O, 
        SWAX, I6), (SWB.O, SWBX, I5), (SWC.O, SWCX, I4), (W1.O, 
        W1X, I15), (W3.O, W3X, I13), (W4.O, W4X, I7)
    4 Output(s)
        (S0_COM_BLIF, O2), (OR_1012, O1), (LDER_COM_BLIF, O0), 
        (ALU_BUS_COM_BLIF, O3)
    11 Product Term(s)

    Output S0_COM_BLIF

        8 Input(s)
            SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, IR7X, SWBX, IR5X
        1 Fanout(s)
            S0.IR
        2 Product Term(s)
        1 GLB Level(s)

        S0_COM_BLIF = STO_Q_BLIF & IR6X & !IR4X & !IR5X & !IR7X & !SWAX
            & !SWBX & !SWCX
            # STO_Q_BLIF & IR4X & !IR5X & !IR7X & !SWAX & !SWBX & !SWCX
            & !IR6X

    Output OR_1012

        7 Input(s)
            W3X, SWAX, STO_Q_BLIF, SWCX, W4X, W1X, SWBX
        1 Fanout(s)
            SW_BUS.IR
        4 Product Term(s)
        1 GLB Level(s)

        OR_1012 = W4X & !STO_Q_BLIF
            # STO_Q_BLIF & SWBX & W1X & !SWCX
            # STO_Q_BLIF & SWCX & W1X & !SWAX & !SWBX
            # STO_Q_BLIF & SWAX & SWBX & W3X & !SWCX

    Output LDER_COM_BLIF

        9 Input(s)
            W3X, SWAX, IR6X, STO_Q_BLIF, SWCX, IR4X, IR7X, SWBX, IR5X
        1 Fanout(s)
            LDER.IR
        3 Product Term(s)
        1 GLB Level(s)

        LDER_COM_BLIF = STO_Q_BLIF & SWAX & SWBX & W3X & !SWCX
            # STO_Q_BLIF & W3X & !IR7X & !SWAX & !SWBX & !SWCX & !IR6X
            # STO_Q_BLIF & IR4X & W3X & !IR5X & !IR7X & !SWAX & !SWBX
            & !SWCX

    Output ALU_BUS_COM_BLIF