untitled.tsu

上载硬部线学校课程设计

Setup and Hold Report:
---------------------

Design Name: UNTITLED
Part Name: ispLSI1032E-100LJ84

  This report lists the setup/hold requirements for all the boundary
  registers in the design


Required Setup and Hold

  Register Name         Data                Clock               Setup(ns)      Hold(ns)
==-------------------------------------------------------------------------------------
  GLB_...BLIF *1        W4                  T1                  -1.90          8.20    
  GLB_...BLIF *1        W4                  MF                  -1.90          8.20    
  GLB_...BLIF *1        W4                  CLR                 -1.90          8.20    
  GLB_...BLIF *1        CLR                 T1                  -2.30          8.60    
  GLB_...BLIF *1        CLR                 MF                  -2.30          8.60    
  GLB_...BLIF *1        CLR                 CLR                 -2.30          8.60    
  GLB_...BLIF *2        CLR                 T1                  -2.00          8.60    
  GLB_...BLIF *2        CLR                 MF                  -2.00          8.60    
  GLB_...BLIF *2        CLR                 CLR                 -2.00          8.60    
==-----------------------------------------------------------------------------------

Index Name Table
==----------------------------------------
    *1  GLB_STO_Q_BLIF
    *2  GLB_RUN_Q_BLIF
==----------------------------------------