halw90p710mac.h

包含8139

#define 	RESTART_AN      	(1 << 9)
#define 	PHY_FULLDUPLEX  	(1 << 8)
#define 	PHY_COL_TEST    	(1 << 7)


// MAC Interrupt Enable Register(MIEN)
#define 	EnRXINTR 			0x00000001  // Enable Interrupt on Receive Interrupt
#define 	EnCRCE   			0x00000002  // Enable CRC Error Interrupt
#define 	EnRXOV   			0x00000004  // Enable Receive FIFO Overflow Interrupt
#define 	EnPTLE   			0x00000008  // Enable Packet Too Long Interrupt
#define 	EnRXGD   			0x00000010  // Enable Receive Good Interrupt
#define 	EnALIE   			0x00000020  // Enable Alignment Error Interrupt
#define 	EnRP     			0x00000040  // Enable Runt Packet on Receive Interrupt
#define 	EnMMP    			0x00000080  // Enable More Missed Packets Interrupt
#define 	EnDFO    			0x00000100  // Enable DMA receive frame over maximum size Interrupt
#define 	EnDEN    			0x00000200  // Enable DMA early notification Interrupt
#define 	EnRDU    			0x00000400  // Enable Receive Descriptor Unavailable Interrupt
#define 	EnRxBErr 			0x00000800  // Enable Receive Bus ERROR interrupt
#define 	EnCFR    			0x00004000  // Enable Control Frame Receive Interrupt
#define 	EnTXINTR 			0x00010000  // Enable Interrupt on Transmit Interrupt
#define 	EnTXEMP  			0x00020000  // Enable Transmit FIFO Empty Interrupt
#define 	EnTXCP   			0x00040000  // Enable Transmit Completion Interrupt
#define 	EnEXDEF  			0x00080000  // Enable Defer Interrupt
#define 	EnNCS    			0x00100000  // Enable No Carrier Sense Interrupt
#define 	EnTXABT  			0x00200000  // Enable Transmit Abort Interrupt
#define 	EnLC     			0x00400000  // Enable Late Collision Interrupt
#define 	EnTDU    			0x00800000  // Enable Transmit Descriptor Unavailable Interrupt
#define 	EnTxBErr 			0x01000000  // Enable Transmit Bus ERROR Interrupt

// PHY Status Register
#define 	AN_COMPLETE     	(1 << 5)

// PHY Auto-negotiation Advertisement Register

#define 	MODE_DR100_FULL   	3
#define 	MODE_DR100_HALF  	2
#define 	MODE_DR10_FULL    	1
#define 	MODE_DR10_HALF    	0


#define 	DR100_TX_FULL   	(1 << 8)
#define 	DR100_TX_HALF   	(1 << 7)
#define 	DR10_TX_FULL    	(1 << 6)
#define 	DR10_TX_HALF    	(1 << 5)
#define 	IEEE_802_3_CSMA_CD   1



//MAC Interrupt Enable Register
#define 	MIEN_EnRXINTR		1
#define 	MIEN_EnCRCE			(1<<1)
#define 	MIEN_EnRXOV			(1<<2)
#define 	MIEN_EnPTLE			(1<<3)
#define 	MIEN_EnRXGD			(1<<4)
#define 	MIEN_EnALIE			(1<<5)
#define 	MIEN_EnRP			(1<<6)
#define 	MIEN_EnMMP			(1<<7)
#define 	MIEN_EnDFO			(1<<8)
#define 	MIEN_EnDEN			(1<<9)
#define 	MIEN_EnRDU			(1<<10)
#define 	MIEN_EnRXBErr		(1<<11)
#define 	MIEN_EnCFR			(1<<14)
#define 	MIEN_EnTXINTR		(1<<16)
#define 	MIEN_EnTXEMP		(1<<17)
#define 	MIEN_EnTXCP			(1<<18)
#define 	MIEN_EnEXDEF		(1<<19)
#define 	MIEN_EnNCS			(1<<20)
#define 	MIEN_EnTXABT		(1<<21)
#define 	MIEN_EnLC			(1<<22)
#define 	MIEN_EnTDU			(1<<23)
#define 	MIEN_EnTxBErr		(1<<24)
//MAC Command Regiser
#define 	MCMDR_RXON			1
#define 	MCMDR_ALP			(1<<1)
#define 	MCMDR_ARP			(1<<2)
#define 	MCMDR_ACP			(1<<3)
#define 	MCMDR_AEP			(1<<4)
#define 	MCMDR_SPCRC			(1<<5)
#define 	MCMDR_TXON			(1<<8)
#define 	MCMDR_NDEF			(1<<9)
#define 	MCMDR_SDPZ			(1<<16)
#define 	MCMDR_EnSQE			(1<<17)
#define 	MCMDR_FDUP			(1<<18)
#define 	MCMDR_EnMDC			(1<<19)
#define 	MCMDR_OPMOD			(1<<20)
#define 	MCMDR_LBK			(1<<21)
//#define 	MCMDR_EnMII			(1<<22)
//#define 	MCMDR_LAN			(1<<23)
#define 	SWR					(1<<24)	


//MAC MII Management Data Control and Address Register
#define  	MIIDA_PHYRAD		1
#define 	MIIDA_PHYAD			(1<<8)
#define  	MIIDA_WR			(1<<16)
#define  	MIIDA_BUSY			(1<<17)
#define  	MIIDA_PreSP			(1<<18)
#define  	MIIDA_MDCON			(1<<19)
#define  	MIIDA_MDCCR			(1<<20)

//FIFO Threshold Adjustment Register
#define  	FIFOTHD_RxTHD		 1
#define  	FIFOTHD_TxTHD		(1<<8)
#define  	FIFOTHD_SWR			(1<<16)
#define  	FIFOTHD_Blength 	(1<<20)
//MAC Interrupt Status Register
#define 	MISTA_RXINTR		1
#define 	MISTA_CRCE			(1<<1)
#define 	MISTA_RXOV			(1<<2)
#define 	MISTA_PTLE			(1<<3)
#define 	MISTA_RXGD			(1<<4)
#define 	MISTA_ALIE			(1<<5)
#define 	MISTA_RP			(1<<6)
#define 	MISTA_MMP			(1<<7)
#define	MISTA_DFOI			(1<<8)
#define	MISTA_DENI			(1<<9)
#define 	MISTA_RDU			(1<<10)
#define 	MISTA_RxBErr		(1<<11)
#define 	MISTA_CFR			(1<<14)
#define 	MISTA_TXINTR		(1<<16)
#define 	MISTA_TXEMP			(1<<17)
#define 	MISTA_TXCP			(1<<18)
#define 	MISTA_EXDEF			(1<<19)
#define 	MISTA_NCS			(1<<20)
#define 	MISTA_TXABT			(1<<21)
#define 	MISTA_LC			(1<<22)
#define 	MISTA_TDU			(1<<23)
#define 	MISTA_TxBErr		(1<<24)

//MAC General Status Register
#define 	MGSTA_CFR			1
#define 	MGSTA_RXHA			(1<<1)
#define 	MGSTA_RFFull		(1<<2) 
#define 	MGSTA_DEF			(1<<4)
#define 	MGSTA_PAU			(1<<5)
#define 	MGSTA_SQE			(1<<6)
#define 	MGSTA_TXHA			(1<<7)


#define 	p710_WriteReg(reg,val,which)	(*((volatile unsigned int *)(MAC_BASE+(which)*0x800+reg)) =(val))		
					 
#define 	p710_ReadReg(reg,which)       	 (*((volatile unsigned int *)(MAC_BASE+reg+(which)*0x800)))
			

#define 	p710_WriteCam0(which,x,lsw,msw) \
			p710_WriteReg(CAM0L+(x)*CAM_ENTRY_SIZE,lsw,which);\
			p710_WriteReg(CAM0M+(x)*CAM_ENTRY_SIZE,msw,which);\


#define 	MDCCR1   				0x00a00000  // MDC clock rating


#define 	RX_DESC_SIZE (3*10)
#define 	TX_DESC_SIZE (10)
#define 	CHECK_SIZE
#define 	PACKET_BUFFER_SIZE 1600
#define 	PACKET_SIZE   1560
#define 	TX_TIMEOUT  (50)
#define 	ETH_ALEN 6

/// 设备接口函数表宏
#define HAL_W90P710MAC_DLL_NETETHER_INTERFACE {W90P710MAC_Find,\
										W90P710MAC_GetResource,\
										W90P710MAC_ReleaseResource,\
										W90P710MAC_Start,\
										W90P710MAC_Stop,\
										W90P710MAC_SendPkt,\
										W90P710MAC_ChipIntEnable,\
										W90P710MAC_ChipIntDisable,\
										W90P710MAC_GetIntType,\
										W90P710MAC_GetPktLen,\
										W90P710MAC_GetPktData,\
										W90P710MAC_HandleOtherIsrType,\
										W90P710MAC_GetMacAddr,\
										W90P710MAC_SetMacAddr,\
										W90P710MAC_LineCheck,\
										W90P710MAC_AddMultiAddr,\
										W90P710MAC_DelMultiAddr}



typedef struct
{	
	unsigned long which;
	unsigned long rx_mode;
	volatile unsigned long cur_tx_entry;
	volatile unsigned long cur_rx_entry;
	volatile unsigned long is_rx_all;
//Test
	unsigned long bInit;
	unsigned long rx_packets;
	unsigned long rx_bytes;
	unsigned long start_time;

	char		plugout;

	volatile unsigned long tx_ptr;
	unsigned long tx_finish_ptr;
	volatile unsigned long rx_ptr;

	unsigned long start_tx_ptr;
	unsigned long start_tx_buf;

	//char aa[100*100];
	unsigned long mcmdr;
	volatile unsigned long start_rx_ptr;
	volatile unsigned long start_rx_buf;
	char 		  devmac[6];
	volatile  	  RXBD   rx_desc[RX_DESC_SIZE]  __attribute__ ((aligned (16)));
	volatile      TXBD   tx_desc[TX_DESC_SIZE]	__attribute__ ((aligned (16)));
	volatile char rx_buf[RX_DESC_SIZE][PACKET_BUFFER_SIZE]	__attribute__ ((aligned (16)));
	volatile char tx_buf[TX_DESC_SIZE][PACKET_BUFFER_SIZE]	__attribute__ ((aligned (16)));
} T_EiStatus;

/// 设备数据表结构
typedef struct{
	//-------------------------系统统一要求的配置项
	T_BSP_DEV_PUB_DATA pub;

	//--------------------------HAL本身需要配置的部分，该部分由HAL设计
	T_UWORD 	vector1;	/// 设备的的第二个中断向量号
	T_VBYTE		*vbpW90P710MACAddr;
	T_BYTE		mac0;
	T_BYTE		mac1;
	T_BYTE		mac2;
	T_BYTE		mac3;
	T_BYTE		mac4;
	T_BYTE		mac5;


	//--------------------------HAL本身不需要配置的部分
	T_EiStatus *p710_priv;		//设备信息结构

}T_HAL_W90P710MAC_DEV_DATA;




#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif //#ifndef _W90P710MAC_H