halw90p710mac.h

包含8139

/*
 * 修改记录：
 *	200600925	创建文件。
 *
 */

/**
 * @file	halW90P710mac.h
 * @brief
 *	<li>功能： W90P710以太网设备HAL相关数据和宏等</li>
 * @date 	200600925
 */

#ifndef _W90P710MAC_H
#define _W90P710MAC_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus */

/****************************** 引用部分 *********************************/
#include <sysTypes.h>	/// 使用系统类型定义
#include <bspPubInfo.h>
#include "dllNetEther.h"

/****************************** 声明部分 *********************************/

T_BOOL W90P710MAC_Find( T_VOID *vpEtherDevData );
T_BOOL W90P710MAC_GetResource( T_VOID *vpEtherDevData );
T_BOOL W90P710MAC_ReleaseResource( T_VOID *vpEtherDevData );
T_BOOL W90P710MAC_Start( T_VOID *vpEtherDevData );
T_BOOL W90P710MAC_Stop( T_VOID *vpEtherDevData );
T_BOOL W90P710MAC_SendPkt( T_VOID *vpEtherDevData, T_CHAR * pktBuf, T_WORD wWtLen );
T_BOOL W90P710MAC_ChipIntEnable( T_VOID *vpEtherDevData );
T_BOOL W90P710MAC_ChipIntDisable( T_VOID *vpEtherDevData );
T_UWORD W90P710MAC_GetIntType( T_VOID *vpEtherDevData, T_UWORD uwVector, T_WORD *wpIntInfo );
T_BOOL W90P710MAC_GetPktLen( T_VOID *vpEtherDevData, T_WORD *pktLen);
T_BOOL W90P710MAC_GetPktData( T_VOID *vpEtherDevData, T_CHAR * bpKtBuf, T_WORD wKtLen );
T_BOOL W90P710MAC_HandleOtherIsrType( T_VOID *vpEtherDevData, T_WORD wIntInfo);
T_BOOL W90P710MAC_GetMacAddr( T_VOID *vpEtherDevData, T_CHAR *bpmacAddr );
T_BOOL W90P710MAC_SetMacAddr( T_VOID *vpEtherDevData, T_CHAR *bpmacAddr );
T_BOOL W90P710MAC_LineCheck( T_VOID *vpEtherDevData, T_WORD *wplineStatus);
T_BOOL W90P710MAC_AddMultiAddr( T_VOID * vpEtherDevData, T_CHAR *bMacAddr, T_VOID * vMultiMacChain);
T_BOOL W90P710MAC_DelMultiAddr( T_VOID * vpEtherDevData, T_CHAR *bMacAddr, T_VOID * vMultiMacChain);

/****************************** 定义部分 *********************************/

/*
 * ASIC Address Definition
 */

#define Base_Addr		0xFFF00000
#define AHB_IO_BASE		Base_Addr
#define APB_IO_BASE		0xFFF80000

/* *********************** */
/* Ethernet BDMA Registers */
/* *********************** */
#define BDMATXCON	(Base_Addr+0x9000)
#define BDMARXCON	(Base_Addr+0x9004)
#define BDMATXPTR	(Base_Addr+0x9008)
#define BDMARXPTR	(Base_Addr+0x900C)
#define BDMARXLSZ	(Base_Addr+0x9010)
#define BDMASTAT	(Base_Addr+0x9014)
#define CAMBASE	(Base_Addr+0x9100)
/*
 * CAM		0x9100 ~ 0x917C
 * BDMATXBUF	0x9200 ~ 0x92FC
 * BDMARXBUF	0x9800 ~ 0x99FC
 */

/* ********************** */
/* Ethernet MAC Registers */
/* ********************** */

#define  MAC_BASE  	(Base_Addr+0x3000)

#define NON_CACHE_FLAG		0x80000000

#define  MAC_OFFSET  	0x0
#define  MAC_0_OFFSET  	MAC_OFFSET


//CAM Registers
#define  CAMCMR			(MAC_OFFSET)   			 //CAM Command Regiser
#define  CAMEN				(MAC_OFFSET+0x4)		 //CAM ennable regiser
#define  CAM0M				(MAC_OFFSET+0x8)		 //CAM1 Most significant Word register
#define  CAM0L				(MAC_OFFSET+0xc)		 //CAM1 Least Significant Word Register
#define  CAM_ENTRY_SIZE	0x8     				 //CAM  entry size
#define  CAM_ENTRIES		0x16    		  		 //CAM  entries

//MAC Regiseters
#define MIEN				(MAC_OFFSET+0xac) 		//MAC Interrupt Enable Register
#define MCMDR				(MAC_OFFSET+0x90) 		//MAC Command Regiser
#define MIID				(MAC_OFFSET+0x94) 		//MII Management Data Register
#define MIIDA				(MAC_OFFSET+0x98) 		//MII Management Data Control and Address Register
#define MPCNT				(MAC_OFFSET+0xb8) 		//Missed Packet Counter Register

//DMA Registers
#define TXDLSA				(MAC_OFFSET+0x88) 		//Transmit Descriptor Link List Start Address Regiser
#define RXDLSA				(MAC_OFFSET+0x8c) 		//Receive Descriptor LInk List Start Addresss Register
#define DMARFC				(MAC_OFFSET+0xa8) 		//DMA Receive Frame Control Register
#define TSDR				(MAC_OFFSET+0xa0) 		//Transmit Start Demand Register
#define RSDR				(MAC_OFFSET+0xa4) 		//Recevie Start Demand Register
#define FIFOTHD			(MAC_OFFSET+0x9c) 		//FIFO Threshold Adjustment Register

//EMC Status Register
#define MISTA				(MAC_OFFSET+0xb0) 		//MAC Interrupter Status Register
#define MGSTA				(MAC_OFFSET+0xb4)		//MAC General Status Register
#define MRPC				(MAC_OFFSET+0xbc)  		//MAC Receive Pauese counter register
#define MRPCC				(MAC_OFFSET+0xc0) 		//MAC Receive Pauese Current Count Regiser
#define MREPC				(MAC_OFFSET+0xc4)  		//MAC Remote pause count retister

//DMA Registers
#define DMARFS				(MAC_OFFSET+0xc8)		//DMA Receive Frame Status Register
#define CTXDSA				(MAC_OFFSET+0xcc) 		//Current Transmit Descriptor Start Addresss Register
#define CTXBSA				(MAC_OFFSET+0xd0) 		//Current Transmit Buffer Start Address Regiser
#define CRXDSA				(MAC_OFFSET+0xd4) 		//Current Receive Descriptor start Address regiser
#define CRXBSA				(MAC_OFFSET+0xd8) 		//Current Receive Buffer Start Address Regiser

//Debug Mode Receive Finite State Machine Registers
#define RXFSM				(MAC_OFFSET+0x200)
#define TXFSM				(MAC_OFFSET+0x204)
#define FSM0				(MAC_OFFSET+0x208)
#define FSM1				(MAC_OFFSET+0x20c)

//Descriptor
typedef struct
{
	volatile unsigned long	SL;
	volatile unsigned long	buffer;
	volatile unsigned long	reserved;
	volatile unsigned long	next;
}RXBD;


typedef struct
{
	volatile unsigned long mode;
	volatile unsigned long buffer;
	volatile unsigned long SL;
	volatile unsigned long next;
}TXBD;


// CAM Command Register(CAMCMR)
#define 	CAM_AUP  			0x0001 	 	// Accept Packets with Unicast Address
#define 	CAM_AMP  			0x0002  	// Accept Packets with Multicast Address
#define 	CAM_ABP  			0x0004  	// Accept Packets with Broadcast Address
#define 	CAM_CCAM 			0x0008  	// 0: Accept Packets CAM Recognizes and Reject Others
                         					// 1: Reject Packets CAM Recognizes and Accept Others
#define 	CAM_ECMP 			0x0010  	// Enable CAM Compare
//ownership bit
#define	RX_OWNERSHIP_CPU	(0x0<<30)
#define	RX_OWNERSHIP_DMA	(2<<30)

#define 	TX_OWNERSHIP_CPU	(0x0<<30)
#define	TX_OWNERSHIP_DMA	(2<<30)

// RX Frame Descriptor's Owner bit
#define 	RXfOwnership_DMA 	0x80000000  // 10 = DMA
#define 	RXfOwnership_CPU 	0x3fffffff  // 00 = CPU

// TX Frame Descriptor's Owner bit
#define 	TXfOwnership_DMA 	0x80000000  // 1 = DMA
#define 	TXfOwnership_CPU 	0x7fffffff  // 0 = CPU

// Tx Frame Descriptor's Control bits
#define 	MACTxIntEn    		0x04
#define 	CRCMode       		0x02
#define 	NoCRCMode     		0x00
#define 	PaddingMode   		0x01
#define 	NoPaddingMode 		0x00

//received descriptor status
#define 	RXDS_RXINTR     	(1<<16) 	//set if reception of packet caused an interrupt condition
#define 	RXDS_CRCE			(1<<17) 	// set if crc error
#define 	RXDS_PTLE			(1<<19) 	//set if received frame longer than 1518 bytes
#define 	RXDS_RXGD			(1<<20) 	// receiving good packet
#define 	RXDS_ALIE			(1<<21) 	//Alignment Error
#define 	RXDS_RP				(1<<22) 	//runt packet
#define 	RXDS_Inverse		(1<<26) 	//current hit entry is setting on inverse mode
#define 	RXDS_PortHit		(1<<27)	 	//port hit
#define 	RXDS_IPHit			(1<<28)		//ip hit
#define 	RXDS_Hit			(1<<29)	 	//hit

//Tx ownership bit
//#define TX_OWNERSHIP_CPU  (0x0<<31)
//#define TX_OWNERSHIP_DMA  (0x1<<31)
//tx mode
#define  	TX_MODE_PAD			 0x1	 	 //pad
#define  	TX_MODE_CRC			(0x1<<1) 	 //crc mode
#define  	TX_MODE_IE			(0x1<<2) 	 //interrupt enable

//Tx status
#define 	TXDS_TXINTR 		(1<<16)		//Interruput on Transmit
#define 	TXDS_DEF			(1<<17)		//Transmit defered
#define 	TXDS_TXCP			(1<<19)		//Transmit Completion
#define 	TXDS_EXDEF			(1<<20)		//exceed deferal
#define 	TXDS_NCS			(1<<21)		//No Carrier Sense Error
#define 	TXDS_TXABT			(1<<22)		//transimtting aborted
#define 	TXDS_LC				(1<<23)		//late collision
#define 	TXDS_TXHA			(1<<24)		//transmitting halted
#define 	TXDS_PAU			(1<<25)		//Paused
#define 	TXDS_SQE			(1<<26)		//SQE error
#define 	TXDS_CCNT			(0xf<<27)	//transmit collision count
//cam command regiser
#define 	CAMCMR_AUP			0x1 		//Accept unicast packet
#define 	CAMCMR_AMP			(0x1<<1) 	//Accpet multicast packet
#define 	CAMCMR_ABP			(0x1<<2) 	//Accept broadcast packet
#define	CAMCMR_CCAM			(0x1<<3) 	//complement CAM
#define 	CAMCMR_ECMP			(0x1<<4) 	//Enable CAM compare


// MAC MII Management Data Control and Address Register(MIIDA)
#define	MDCCR    			0x00300000  // MDC clock rating
#define 	PHYAD    			0x00000100  // PHY Address
#define 	PHYWR    			0x00010000  // Write Operation
#define 	PHYBUSY  			0x00020000  // Busy Bit
#define 	PHYPreSP 			0x00040000  // Preamble Suppress

// PHY(DM9161) Register Description
#define 	PHY_CNTL_REG    	0x00
#define 	PHY_STATUS_REG  	0x01
#define 	PHY_ID1_REG     	0x02
#define 	PHY_ID2_REG     	0x03
#define 	PHY_ANA_REG     	0x04
#define 	PHY_ANLPA_REG   	0x05
#define 	PHY_ANE_REG     	0x06

#define 	PHY_DSC_REG     	0x10
#define 	PHY_DSCS_REG    	0x11
#define 	PHY_10BTCS_REG  	0x12
#define 	PHY_SINT_REG    	0x15
#define 	PHY_SREC_REG    	0x16
#define 	PHY_DISC_REG   		0x17

//PHY Control Register
#define 	RESET_PHY       	(1 << 15)
#define 	ENABLE_LOOPBACK 	(1 << 14)
#define 	DR_100MB        	(1 << 13)
#define 	ENABLE_AN       	(1 << 12)
#define 	PHY_MAC_ISOLATE 	(1 << 10)