spi.h

台湾亚信电子ASIX11015的SPI口驱动,很适合接当今流行的SPI口.希望和大家一起努力!

/*
 *********************************************************************************
 *     Copyright (c) 2005	ASIX Electronic Corporation      All rights reserved.
 *
 *     This is unpublished proprietary source code of ASIX Electronic Corporation
 *
 *     The copyright notice above does not evidence any actual or intended
 *     publication of such source code.
 *********************************************************************************
 */
/*================================================================================
 * Module Name : spi.h
 * Purpose     : A header file of spi.c. It defines register address and bits.
 * Author      : Robin Lee
 * Date        : 2005-01-11
 * Notes       :
 * $Log: spi.h,v $
 * Revision 1.1  2006/04/07 11:39:02  robin6633
 * no message
 *
 *================================================================================
 */
#ifndef SPI_H
#define SPI_H

/* INCLUDE FILE DECLARATIONS */
#include	"spi_cfg.h"


/* NAMING CONSTANT DECLARATIONS */
/* SPI register */
#define	SPIRBR					0x00	// SPI Receive Buffer Register
#define	SPITBR					0x04	// SPI Transmit Buffer Register
#define	SPICTRLR				0x08	// SPI Control Register
#define	SPICMDR					0x09	// SPI Command Register
#define	SPIBRR					0x0A	// SPI Baud Rate Register
#define	SPISSR					0x0B	// SPI Slave Select Register
#define	SPIISR					0x0C	// SPI Interrupt Status Register
#define	SPIIER					0x0D	// SPI Interrupt Enable Register
#define	SPISCR					0x0E	// SPI Slave Command Register
#define	SPISB					0x10	// SPI Slave Buffer Register

/* SPICTRLR */
#define	SPI_SSP_HIGH			BIT0	// slave select is high active
#define	SPI_SSP_LOW				0		// slave select is low active
#define	SPI_CPHA_BEG			BIT1	// spi first clock edge is issued at the beginning of transfer cycle
#define	SPI_CPHA_HALF			0		// spi first clock edge is issued one-half cycle of transfer cycle
#define	SPI_CPOL_LOW			BIT2	// clock active low
#define	SPI_CPOL_HIGH			0		// clock active high
#define	SPI_LSB_FIRST			BIT3	// the LSB is sent first
#define	SPI_MSB_FIRST			0		// the MSB is sent first
#define	SPI_ENB					BIT4	// spi module enable
#define	SPI_DISB				0		// spi module disable
#define	SPI_SS_AUTO				BIT5	// slave select signal generated automatically
#define	SPI_SS_NORM				0		// slave select signal generated by SPISSR bits
#define	SPI_MST_SEL				BIT6	// spi master mode
#define	SPI_SLV_SEL				0		// spi slave mode
#define	SPI_SSO_ENB				BIT7	// enable driving slave select signal
#define	SPI_SSO_DISB			0		// put slave select signal to tri-state

/* SPICMDR */
#define	SPI_LOST_CLK			BIT5	// suppress the last clock
#define	SPI_LONG_LEN			BIT6	// the current transfer length is small than desired length
#define	SPI_NORMAL_LEN			0		// the current transfer length is the desired length
#define	SPI_GO_BSY				BIT7	// start a transfer

/* SPIBRR */
#define	SLAVE_SEL_0				~BIT0	// slave select signal used on bit0
#define	SLAVE_SEL_1				~BIT1	// slave select signal used on bit1
#define	SLAVE_SEL_2				~BIT2	// slave select signal used on bit2
#define	SLAVE_SEL_3				~BIT3	// slave select signal used on bit3
#define	SLAVE_SEL_4				~BIT4	// slave select signal used on bit4
#define	SLAVE_SEL_5				~BIT5	// slave select signal used on bit5
#define	SLAVE_SEL_6				~BIT6	// slave select signal used on bit6
#define	SLAVE_SEL_7				~BIT7	// slave select signal used on bit7

/* SPIISR */
#define	SPI_MCF					BIT0	// spi master mode interrupt flag
#define	SPI_SCF					BIT4	// spi slave mode interrupt flag

/* SPIIER */
#define	SPI_STCFIE				BIT0	// spi master mode interrupt enable
#define	SPI_SRCFIE				BIT4	// spi slave mode interrupt enable

/* SPISCR */
#define	SPI_SLV_RDY				BIT0	// spi slave ready

/* SPI Definition */
#define	SPI_MST_XMIT			BIT0
#define	SPI_MST_RCVR			BIT1
#define	SPI_SLV_XMIT			BIT2
#define	SPI_SLV_RCVR			BIT3

/* SPI Action Flag */
#define	SPI_BUSY				BIT0	// spi bus busy flag

/* SPI Slave Command */
#define SPI_SLV_RSR				0				// read status register command
#define	SPI_SLV_RDR				BIT4			// read data register command
#define	SPI_SLV_SRSFR			BIT5			// single read SFR command
#define	SPI_SLV_SWSFR			BIT7+BIT5		// single write SFR command
#define	SPI_SLV_IRSFR			BIT5+BIT4		// indirect read SFR command
#define	SPI_SLV_IWSFR			BIT7+BIT5+BIT4	// indirect write SFR command
#define	SPI_SLV_BRMEM			BIT6			// burst read memory command
#define	SPI_SLV_BWMEM			BIT7+BIT6		// burst write memory command


/* MACRO DECLARATIONS */


/* TYPE DECLARATIONS */


/* GLOBAL VARIABLES */


/* EXPORTED SUBPROGRAM SPECIFICATIONS */
void	SPI_Setup(U8_T ctrlCmd, U8_T intrEnb, U8_T baudrate, U8_T slvSel);
void	SPI_Func(void);
void	SPI_MstXmit(U8_T *ptSpiTxPkt, U8_T xmitBit, U8_T spiCmd);
void	SPI_SlvXmit(U8_T spiSlvCmd);
BOOL	SPI_FlagChk(U8_T chkBit);
void	SPI_FlagEnb(U8_T enbBit);
void	SPI_FlagClr(U8_T clrBit);
void	SPI_GetData(U8_T *ptBuf);
void	SPI_Post(void);
void	SPI_Cmd(U8_T cmdType, U8_T spiCmdIndex, U8_T *spiData);


#endif /* End of SPI_H */