📄 reg.h
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#ifndef _reg_h_
#define _reg_h_
//-----------------------------------------------------------------------------
// CP220x_REG.h
//-----------------------------------------------------------------------------
// Copyright 2006 Silicon Laboratories, Inc.
// http://www.silabs.com
//
// Program Description:
//
// Header File for CP220x Register Definitions.
//-----------------------------------------------------------------------------
// Indirect Register Definitions
//-----------------------------------------------------------------------------
#define MACCN 0x00 // MAC Control
#define MACCF 0x01 // MAC Configuration
#define IPGT 0x02 // Back-to-Back Interpacket Delay
#define IPGR 0x03 // Non-Back-to-Back Interpacket Delay
#define CWMAXR 0x04 // Collision Window and Maximum Retransmit
#define MAXLEN 0x05 // Maximum Frame Length
#define MACAD0 0x10 // MAC Address 0
#define MACAD1 0x11 // MAC Address 1
#define MACAD2 0x12 // MAC Address 2
//-----------------------------------------------------------------------------
// Direct Register Definitions
//-----------------------------------------------------------------------------
#define RAMADDRH 0x08 // RAM Address Pointer High Byte
#define RAMADDRL 0x09 // RAM Address Pointer Low Byte
#define RAMRXDATA 0x02 // RXFIFO RAM Data Register
#define RAMTXDATA 0x04 // TXBUFF RAM Data Register
#define FLASHADDRH 0x69 // Flash Address Pointer High Byte
#define FLASHADDRL 0x68 // Flash Address Pointer Low Byte
#define FLASHAUTORD 0x05 // Flash Autoread w/ increment
#define FLASHDATA 0x06 // Flash Read/Write Data Register
#define FLASHKEY 0x67 // Flash Lock and Key
#define FLASHERASE 0x6A // Flash Erase
#define FLASHSTA 0x7B // Flash Status
#define MACADDR 0x0A // MAC Address Pointer
#define MACDATAH 0x0B // MAC Data Register High Byte
#define MACDATAL 0x0C // MAC Data Register Low Byte
#define MACRW 0x0D // MAC Read/Write Initiate
#define regINT0 0x63 // Interrupt Status Register 0 (Self-Clearing)
#define INT0RD 0x76 // Interrupt Status Register 0 (Read-Only)
#define INT0EN 0x64 // Interrupt Enable Register 0
#define regINT1 0x7F // Interrupt Status Register 1 (Self-Clearing)
#define INT1RD 0x7E // Interrupt Status Register 1 (Read-Only)
#define INT1EN 0x7D // Interrupt Enable Register 1
#define VDMCN 0x13 // VDD Monitor Control Register
#define SWRST 0x75 // Software Reset Register
#define RSTSTA 0x73 // Reset Source Status Register
#define RSTEN 0x72 // Reset Enable Register
#define IOPWR 0x70 // Port Input/Output Power
#define OSCPWR 0x7C // Oscillator Power
#define RXFILT 0x10 // Receive Filter Configuraton
#define RXCN 0x11 // Receive Control
#define RXSTA 0x12 // Receive Status
#define RXAUTORD 0x01 // Receive Autoread w/ increment
#define RXHASHH 0x0E // Receive Hash Table High Byte
#define RXHASHL 0x0F // Receive Hash Table Low Byte
#define CPINFOH 0x1D // Current RX Packet Information High Byte
#define CPINFOL 0x1E // Current RX Packet Information Low Byte
#define CPLENH 0x1F // Current RX Packet Length High Byte
#define CPLENL 0x20 // Current RX Packet Length Low Byte
#define CPADDRH 0x21 // Current RX Packet Address High Byte
#define CPADDRL 0x22 // Current RX Packet Address Low Byte
#define CPTLB 0x1A // Current RX Packet TLB Number
#define TLBVALID 0x1C // TLB Valid Indicators
#define TLB0INFOH 0x23 // TLB0 Information High Byte
#define TLB0INFOL 0x24 // TLB0 Information Low Byte
#define TLB0LENH 0x25 // TLB0 Length High Byte
#define TLB0LENL 0x26 // TLB0 Length Low Byte
#define TLB0ADDRH 0x27 // TLB0 Address High Byte
#define TLB0ADDRL 0x28 // TLB0 Address Low Byte
#define TLB1INFOH 0x29 // TLB1 Information High Byte
#define TLB1INFOL 0x2A // TLB1 Information Low Byte
#define TLB1LENH 0x2b // TLB1 Length High Byte
#define TLB1LENL 0x2C // TLB1 Length Low Byte
#define TLB1ADDRH 0x2D // TLB1 Address High Byte
#define TLB1ADDRL 0x2E // TLB1 Address Low Byte
#define TLB2INFOH 0x2F // TLB2 Information High Byte
#define TLB2INFOL 0x30 // TLB2 Information Low Byte
#define TLB2LENH 0x31 // TLB2 Length High Byte
#define TLB2LENL 0x32 // TLB2 Length Low Byte
#define TLB2ADDRH 0x33 // TLB2 Address High Byte
#define TLB2ADDRL 0x34 // TLB2 Address Low Byte
#define TLB3INFOH 0x35 // TLB3 Information High Byte
#define TLB3INFOL 0x36 // TLB3 Information Low Byte
#define TLB3LENH 0x37 // TLB3 Length High Byte
#define TLB3LENL 0x38 // TLB3 Length Low Byte
#define TLB3ADDRH 0x39 // TLB3 Address High Byte
#define TLB3ADDRL 0x3A // TLB3 Address Low Byte
#define TLB4INFOH 0x3B // TLB4 Information High Byte
#define TLB4INFOL 0x3C // TLB4 Information Low Byte
#define TLB4LENH 0x3D // TLB4 Length High Byte
#define TLB4LENL 0x3E // TLB4 Length Low Byte
#define TLB4ADDRH 0x3F // TLB4 Address High Byte
#define TLB4ADDRL 0x40 // TLB4 Address Low Byte
#define TLB5INFOH 0x41 // TLB5 Information High Byte
#define TLB5INFOL 0x42 // TLB5 Information Low Byte
#define TLB5LENH 0x43 // TLB5 Length High Byte
#define TLB5LENL 0x44 // TLB5 Length Low Byte
#define TLB5ADDRH 0x45 // TLB5 Address High Byte
#define TLB5ADDRL 0x46 // TLB5 Address Low Byte
#define TLB6INFOH 0x47 // TLB6 Information High Byte
#define TLB6INFOL 0x48 // TLB6 Information Low Byte
#define TLB6LENH 0x49 // TLB6 Length High Byte
#define TLB6LENL 0x4A // TLB6 Length Low Byte
#define TLB6ADDRH 0x4B // TLB6 Address High Byte
#define TLB6ADDRL 0x4C // TLB6 Address Low Byte
#define TLB7INFOH 0x4D // TLB7 Information High Byte
#define TLB7INFOL 0x4E // TLB7 Information Low Byte
#define TLB7LENH 0x4F // TLB7 Length High Byte
#define TLB7LENL 0x50 // TLB7 Length Low Byte
#define TLB7ADDRH 0x51 // TLB7 Address High Byte
#define TLB7ADDRL 0x52 // TLB7 Address Low Byte
#define RXFIFOHEADH 0x17 // Receive Buffer Head Pointer High Byte
#define RXFIFOHEADL 0x18 // Receive Buffer Head Pointer Low Byte
#define RXFIFOTAILH 0x15 // Receive Buffer Tail Pointer High Byte
#define RXFIFOTAILL 0x16 // Receive Buffer Tail Pointer Low Byte
#define RXFIFOSTA 0x5B // Receive Buffer Status
#define TXSTARTH 0x59 // Transmit Data Starting Address High Byte
#define TXSTARTL 0x5A // Transmit Data Starting Address Low Byte
#define TXAUTOWR 0x03 // Transmit Data Autowrite
#define TXENDH 0x57 // Transmit Data Ending Address High Byte
#define TXENDL 0x58 // Transmit Data Ending Address Low Byte
#define TXCN 0x53 // Transmit Control
#define TXPAUSEH 0x55 // Transmit Pause High Byte
#define TXPAUSEL 0x56 // Transmit Pause Low Byte
#define TXBUSY 0x54 // Transmit Busy Indicator
#define TXSTA6 0x5C // Transmit Status Vector 6
#define TXSTA5 0x5D // Transmit Status Vector 5
#define TXSTA4 0x5E // Transmit Status Vector 4
#define TXSTA3 0x5F // Transmit Status Vector 3
#define TXSTA2 0x60 // Transmit Status Vector 2
#define TXSTA1 0x61 // Transmit Status Vector 1
#define TXSTA0 0x62 // Transmit Status Vector 0
#define PHYCN 0x78 // Physical Layer Control
#define PHYCF 0x79 // Physical Layer Configuration
#define PHYSTA 0x80 // Physical Layer Status
#define TXPWR 0x7A // Transmitter Power Register
//-----------------------------------------------------------------------------
// Bit Definitions
//-----------------------------------------------------------------------------
// TLB0INFOH Bit Definitions
#define RXVALID 0x80
#define RXVLAN 0x40
#define RXUNSUP 0x20
#define RXPCF 0x10
#define RXCF 0x08
#define RXADATA 0x04
#define BCAST 0x02
#define MCAST 0x01
// TLB0INFOL Bit Definitions
#define RXOK 0x80
#define LENGTH 0x40
#define LENERR 0x20
#define CRCERR 0x10
#define RXVLT 0x08
#define RXLEN 0x02
#define RXDROP 0x01
// INT0 Bit Definitions
#define EEOPINT 0x80
#define ERXEINT 0x40
#define ESELFINT 0x20
#define EOSCINT 0x10
#define EFLWEINT 0x08
#define ETXINT 0x04
#define ERXFINT 0x02
#define ERXINT 0x01
// INT0EN Bit Definitions
#define EOPINT 0x80
#define RXEINT 0x40
#define SELFINT 0x20
#define OSCINT 0x10
#define FLWEINT 0x08
#define TXINT 0x04
#define RXFINT 0x02
#define RXINT 0x01
// INT1 Bit Definitions
#define WAKEINT 0x20
#define LINKINT 0x10
#define JABINT 0x08
#define ANFINT 0x04
#define RFINT 0x02
#define ANCINT 0x01
// INT1EN Bit Definitions
#define EWAKEINT 0x20
#define ELINKINT 0x10
#define EJABINT 0x08
#define EANFINT 0x04
#define ERFINT 0x02
#define EANCINT 0x01
// RXCN Bit Definitions
#define RXINH 0x08
#define RXCLRV 0x04
#define RXSKIP 0x02
#define RXCLEAR 0x01
// TXCN Bit Definitions
#define OVRRIDE 0x80
#define CRCENOV 0x20
#define PADENOV 0x10
#define TXPPKT 0x08
#define BCKPRES 0x04
#define FDPLXOV 0x02
#define TXGO 0x01
// PHYCN Bit Definitions
#define PHYEN 0x80
#define PHYTXEN 0x40
#define PHYRXEN 0x20
#define DPLXMD 0x10
#define LBMD 0x08
#define LPRFAULT 0x04
#define POLREV 0x02
#define LINKSTA 0x01
// PHYCF Bit Definitions
#define SMSQ 0x80
#define LINKINTG 0x40
#define JABBER 0x20
#define AUTONEG 0x10
#define ADRFAULT 0x08
#define ADPAUSE 0x04
#define AUTOPOL 0x02
#define REVPOL 0x01
// MACCN Bit Definitions
#define RANDRST 0x4000
#define LOOPBCK 0x0010
#define TXPAUSE 0x0008
#define RXPAUSE 0x0004
#define PASSALL 0x0002
#define RCVEN 0x0001
// MACCF Bit Definitions
#define ABORTD 0x4000
#define EBBPD 0x2000
#define EBD 0x1000
#define RLPRE 0x0200
#define PUREPRE 0x0100
#define PADMD1 0x0080
#define PADMD0 0x0040
#define PADEN 0x0020
#define CRCEN 0x0010
#define PHEADER 0x0008
#define LENCHK 0x0002
#define FLLDPLX 0x0001
#define OSC_ERROR 0x01 // Error Return Codes
#define CAL_ERROR 0x02
#define MEM_ERROR 0x04
#define FLASH_ERROR 0x08
#define MAC_ERROR 0x10
#define LINK_ERROR 0x20
#define DATA_ERROR 0x40
#endif
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