gmac_mod.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

///////////////////////////////////////////////////////////////////////////////
//
//      Project:  RGMII/Gigabit Ethernet MAC
//      Version:  1.0
//      File   :  gmac_mod.v
//
//      Company:  Xilinx
// Contributors:  Mary Low
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// Top Level RGMII Gigabit Ethernet MAC
// Author: Mary Low
//
// Description: This is the module declaration for the 1-Gig Ethernet MAC
//
///////////////////////////////////////////////////////////////////////////////


`timescale 1 ps / 1 ps

/****************************************************************************
 * Component Declaration for gmac (the 1Gb/E MAC core).
 ****************************************************************************/
 
module GMAC
(
    // Reset signal
    RESET,
    
    // Client receiver interface
    RX_CLK,
    RX_GOOD_FRAME,
    RX_BAD_FRAME,
    RX_DATA,
    RX_DATA_VALID,
    RX_STATISTICS_VECTOR, 
    RX_STATISTICS_VALID,  
    
    // Client transmitter interface
    TX_CLK,
    TX_DATA,
    TX_DATA_VALID,
    TX_UNDERRUN,
    TX_ACK,
    TX_RETRANSMIT,
    TX_COLLISION,
    TX_IFG_DELAY,
    TX_STATISTICS_VECTOR,
    TX_STATISTICS_VALID,
    
    // MAC control interface
    PAUSE_REQ,
    PAUSE_VAL,
    
    // GMII interface
    GTX_CLK,       
    GMII_COL,      
    GMII_CRS,      
    GMII_TXD,       
    GMII_TX_EN,    
    GMII_TX_ER,    
    GMII_TX_CLK,   
    GMII_RXD,       
    GMII_RX_DV,    
    GMII_RX_ER,    
    GMII_RX_CLK,   
    
    // MDIO interface
    MDIO_IN,
    MDIO_OUT,
    MDIO_TRI,
    MDC,
    
    // Host interface
    HOST_CLK,
    HOST_OPCODE,
    HOST_ADDR,
    HOST_WR_DATA,
    HOST_REQ,
    HOST_MIIM_SEL,
    HOST_RD_DATA,
    HOST_MIIM_RDY
);


// synthesis syn_black_box                             -- Synplicity attribute
// synthesis attribute BOX_TYPE of GMAC is "BLACK_BOX" -- XST attribute



//***********************************Port Declarations*************************

 
    // Reset signal 
    input           RESET;
    
     // Client receiver interface   
    output          RX_CLK;
    output          RX_GOOD_FRAME;
    output          RX_BAD_FRAME;
    output [7 : 0]  RX_DATA;
    output          RX_DATA_VALID;
    output [22 : 0] RX_STATISTICS_VECTOR;
    output          RX_STATISTICS_VALID;
    
     // Client transmitter interface   
    output          TX_CLK;
    input  [7 : 0]  TX_DATA;
    input           TX_DATA_VALID;
    input           TX_UNDERRUN;
    output          TX_ACK;
    output          TX_RETRANSMIT;
    output          TX_COLLISION;
    input  [7 : 0]  TX_IFG_DELAY;
    output [28 : 0] TX_STATISTICS_VECTOR;
    output          TX_STATISTICS_VALID;
    
     // MAC control interface   
    input           PAUSE_REQ;
    input [15 : 0]  PAUSE_VAL;
    
     // GMII interface
    input           GTX_CLK;       
    input           GMII_COL;      
    input           GMII_CRS;      
    output [7 : 0]  GMII_TXD;      
    output          GMII_TX_EN;    
    output          GMII_TX_ER;    
    output          GMII_TX_CLK;   
    input  [7 : 0]  GMII_RXD;      
    input           GMII_RX_DV;    
    input           GMII_RX_ER;    
    input           GMII_RX_CLK;   

     // MDIO interface
    input           MDIO_IN;
    output          MDIO_OUT;
    output          MDIO_TRI;
    output          MDC;
    
     // Host interface   
    input 	    HOST_CLK;
    input [1 : 0]   HOST_OPCODE;
    input [9 : 0]   HOST_ADDR;
    input [31 : 0]  HOST_WR_DATA;
    input 	    HOST_REQ;
    input 	    HOST_MIIM_SEL;
    output [31 : 0] HOST_RD_DATA;
    output 	    HOST_MIIM_RDY;

endmodule // gmac