sync_reset.v

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///////////////////////////////////////////////////////////////////////////////
//
//      Project:  RGMII Adaptation Module
//      Version:  1.0
//      File   :  sync_reset.v
//
//      Company:  Xilinx
// Contributors:  Ting Kao, Mary Low
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
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//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// Reset quasi-synchroniser
// Author: Xilinx Inc.
// Translated to Verilog by Nigel Gulstone
//
// Description: This reset synchronizer was derived from:
//              http://www.xilinx.com/support/techxclusives/global/techX19.htm
//              It is used to generate a reset signal which has a falling edge
//              synchronous with CLK; this allows predictable reset recovery
//              even using the asynchronous reset pins of register primitives
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1 ps	

module SYNC_RESET 
(
    RESET_IN, 
    CLK,      
    
    RESET_OUT 
);         


//***********************************Port Declarations**************************

    input           RESET_IN;       // Active high asynchronous reset
    input           CLK;            // clock to be sync'ed to
    
    output          RESET_OUT;      // "Synchronised" reset signal
 
    
//*************************Internal Register Declarations***********************

    reg     [0:3]   shift_register_r; 


//*********************************Main Body of Code****************************


    // This is the synchronizer. Its a 4 stage shift register with an asynch 
    //  preset. The 4 registers should pack into 2 slices.
    always @(posedge CLK or posedge RESET_IN)
        if(RESET_IN)    shift_register_r    <=  4'hF;
        else            shift_register_r    <=  {1'b0,shift_register_r[0:2]};
    
    
    assign  RESET_OUT   =   shift_register_r[3];   
    
         
endmodule