rgmii_tx.v

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///////////////////////////////////////////////////////////////////////////////
//
//      Project:  RGMII Adaptation Module
//      Version:  1.0
//      File   :  rgmii_tx.v
//
//      Company:  Xilinx
// Contributors:  Ting Kao, Mary Low
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// RGMII Transmit component
// Author: Ting Kao
// Translated to Verilog by Nigel Gulstone
//
// Description:  This module converts GMII tranmissions to RGMII.  See 
//               RGMII_spec for details.
//
//               The RGMII interface uses fewer data and control signals than 
//               GMII by multiplexing and using both edges of the clock.  The 
//               control signals GMII_TX_EN and GMII_TX_ER are encoded into
//               RGMII_TX_CTL and valid on both pos and neg edge of the clock
//               Similarily, the data signals RGMII_TXD are valid on both pos
//               and neg edge of the clock.
//
//               To achieve this function, the design uses the DDR IOB
//               registers  of the FPGA.  Instead of having RGMII_TX<3:0> and
//               RGMII_TX_CTL as outputs, this module generates
//               RGMII_TX_RISING<3:0>, RGMII_TX_FALLING<3:0>,
//               RGMII_TX_CTL_RISING and RGMII_TX_CTL_FALLING as outputs. These
//               Rising and Falling  versions of the RGMII bus should be
//               connected to the appropriate DDR ports.
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1 ps	

module RGMII_TX
(
    //General Signals
    RESET,                 
    CLK,                   
    
    
    //RGMII signals (Output)
    RGMII_TX_CTL_RISING,    
    RGMII_TX_CTL_FALLING,   
    RGMII_TXD_RISING,       
    RGMII_TXD_FALLING,      

    
    //GMII signals (Input)
    GMII_TXD,              
    GMII_TX_EN,            
    GMII_TX_ER,            
    
    
    //Configuration and Indicator signals
    SPEED_IS_10_100,       
    TRANSMITTING          
    
);


//***********************************Port Declarations*************************


    //General Signals
    input               RESET;                  // Global Asynchronous Reset.
    input               CLK;                    // GMII/MII CLK 125/25/2.5Mhz
    
    
    //RGMII signals (Output)
    output              RGMII_TX_CTL_RISING;    // To pos clock reg of FDDRRSE 
    					        // of RGMII_TX_CTL
    output              RGMII_TX_CTL_FALLING;   // To pos clock reg of FDDRRSE 
    						// of RGMII_TX_CTL
    output      [3:0]   RGMII_TXD_RISING;       // To pos clock reg of FDDRRSE 
    						// of RGMII_TXD
    output      [3:0]   RGMII_TXD_FALLING;      // To pos clock reg of FDDRRSE 
    						// of RGMII_TXD

    
    //GMII signals (Input)
    input       [7:0]   GMII_TXD;               // TXD from GMII
    input               GMII_TX_EN;             // TX_EN from GMII
    input               GMII_TX_ER;             // TX_ER from GMII
    
    
    //Configuration and Indicator signals
    input               SPEED_IS_10_100;        // If "1", medium is at 10 or 
    						// 100Mhz
    
    output              TRANSMITTING;           // Module transmitting data 

  
//*************************External Register Declarations**********************    

    reg                 RGMII_TX_CTL_RISING;
    reg                 RGMII_TX_CTL_FALLING;
    reg                 TRANSMITTING;
    

//*************************Internal Register Declarations**********************
  
    reg     [7:0]       txd_rising_r;
    reg     [7:0]       txd_falling_r;
    reg                 tx_err_rising_r;
    

//*********************************Wire Declarations***************************
 
    wire    [3:0]       txd_falling_mux_c;
    
    
//*********************************Main Body of Code***************************


    
    //___________________________GMII to RGMII data conversion_________________


    //Register the GMII data on the rising edge
    always @(posedge CLK or posedge RESET)
        if(RESET)   txd_rising_r    <=  8'h00;
        else        txd_rising_r    <=  GMII_TXD;
        
  
  
    //Register the rising edge registered data on the falling edge. We are
    // trying to achieve a specific phase relationship with this registering 
    // scheme.
    always @(negedge CLK or posedge RESET)
        if(RESET)   txd_falling_r   <=  8'h00;
        else        txd_falling_r   <=  txd_rising_r;
   
                                                            
    
    //Select the nibble that will be sampled for the output based on the speed
    // of the ethernet connection. 10_100 connections use a different scheme
    // for data transmission than Gigabit ethernet. See the specification 
    // for more details.
    assign txd_falling_mux_c = SPEED_IS_10_100?txd_falling_r[3:0]:txd_falling_r[7:4];
   

    //Connect the Rising edge DDR to the rising edge signal, and the falling
    // edge DDR to the falling edge signal
    assign   RGMII_TXD_RISING    =   txd_rising_r[3:0];
    assign   RGMII_TXD_FALLING   =   txd_falling_mux_c;
   
   
    
    //_____________________GMII to RGMII control conversion____________________
    
    
    
    //Register the GMII control signals on the rising edge. Note that we
    // also form the ERR signal here from the ER an EN signals. See the 
    // specification for details
    always @(posedge CLK or posedge RESET)
        if(RESET)
            begin
                    RGMII_TX_CTL_RISING     <=  1'b0;
                    tx_err_rising_r         <=  1'b0;
            end
        else
            begin   
                    RGMII_TX_CTL_RISING     <=  GMII_TX_EN;
                    tx_err_rising_r         <=  GMII_TX_ER ^ GMII_TX_EN; 
            end

    
    
    //Register tx_err again on the falling edge. Note that the source
    // of the signal are the rising edge registers. This is neccessary to 
    // produce the phase relationship we need.
    always @(negedge CLK or posedge RESET)
        if(RESET)   RGMII_TX_CTL_FALLING    <=  1'b0;
        else        RGMII_TX_CTL_FALLING    <=  tx_err_rising_r;
            
                                                     

    //_____________________Generate the 'Transmitting' Signal__________________
    
    
    
    //Indicate when data is being transmitted through RGMII layers.
    always @(posedge CLK or posedge RESET)
        if(RESET)                           TRANSMITTING    <=  1'b0;
        else if(GMII_TX_EN)                 TRANSMITTING    <=  1'b1;
        else if(!GMII_TX_EN & !GMII_TX_ER)  TRANSMITTING    <=  1'b0;
    
   
endmodule