rgmii_rx.v

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///////////////////////////////////////////////////////////////////////////////
//
//      Project:  RGMII Adaptation Module
//      Version:  1.0
//      File   :  rgmii_rx.vhd
//
//      Company:  Xilinx
// Contributors:  Ting Kao, Mary Low
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// RGMII Receive component
// Author: Ting Kao
// Translated to Verilog by Nigel Gulstone
//
// Description: The module takes the data and control latched on the rising
//              and falling edge of the clock and "unfold" it to the standard 
//              GMII interface.
//
//      1. The module takes the following as inputs:
//         RGMII_RX_CTL_RISING, RGMII_RX_CTL_FALLING, RGMII_RXD_RISING, 
//         RGMII_RXD_FALLING where XXX_RISING is data latched on the 
//         rising edge of the clock and XXX_FALLING is the data latched 
//         on the falling edge of the clock.  These signals are outputs 
//         of the FDDRRSE, an double data rate input register to be 
//         instantiated at the top level.
//
//      2. For 1Gpbs, RXD of RGMII is a 4 bit bus which needs to be
//         unfolded into the 8bit GMII bus.   RXD<3:0> are latched on the
//         rising edge of the clock while RXD<7:4> are latched on the falling
//         edge. The resulting 8 bits are sent to GMII at 125Mhz.
//                  
//         For 10/100 Mbps, both RGMII and MII are 4 bit buses. RXD<3:0> is
//         latched on rising and falling edge of the first clock.  RXD<7:4> is
//         latched on the rising and falling edge of the subsequent clock. 
//         The data is simply passed through to the MII interface.
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1 ps	

module RGMII_RX
(
    //General Signals
    RESET,                    
    RX_CLK,                   
    
    
    //RGMII Interface (Input)
    RGMII_RX_CTL_RISING,      
    RGMII_RX_CTL_FALLING,     
    RGMII_RXD_RISING,         
    RGMII_RXD_FALLING,        
                              
    
    //GMII Interface (Output)
    GMII_RXD,                 
    GMII_RX_DV,               
    GMII_RX_ER,               


    //Indicator Signals    
    RGMII_RX_SPEED,           
    RGMII_RX_DUPLEX,          
    RGMII_LINK,               
    RECEIVING                 

);


//***********************************Port Declarations*************************

    //General Signals
    input           RESET;                  // Global Asynchronous Reset.
    input           RX_CLK;                 // RGMII RX_CLK.
    
    
    //RGMII Interface (Input)
    input           RGMII_RX_CTL_RISING;    // received from FDDRRSE of RGMII_RX_CTL
    input           RGMII_RX_CTL_FALLING;   // received from FDDRRSE of RGMII_RX_CTL
    input   [3:0]   RGMII_RXD_RISING;       // received from FDDRRSE of RGMII_RXD
    input   [3:0]   RGMII_RXD_FALLING;      // received from FDDRRSE of RGMII_RXD
                                                 // 1 = medium at 10Mhz or 100Mhz
    
    //GMII Interface (Output)
    output  [7:0]   GMII_RXD;               // GMII_RXD 
    output          GMII_RX_DV;             // GMII_RX_DV
    output          GMII_RX_ER;             // GMII_RX_ER


    //Indicator Signals    
    output  [1:0]   RGMII_RX_SPEED;         // optional PHY speed status
    output          RGMII_RX_DUPLEX;        // optional PHY duplex status
    output          RGMII_LINK;             // optional PHY Link status
    output          RECEIVING;              // Receiving data

    
//*************************External Register Declarations********************** 

    reg             GMII_RX_ER;
    reg             GMII_RX_DV;
    reg     [7:0]   GMII_RXD;
    
    reg             RECEIVING;
    reg     [1:0]   RGMII_RX_SPEED;
    reg             RGMII_RX_DUPLEX;
    reg             RGMII_LINK;
    
   
//*************************Internal Register Declarations**********************

    reg     [7:0]   rxd_r;
    reg     [7:0]   rxd_1_r;
    
    reg             rx_dv_r;
    reg             rx_dv_1_r;
    
    reg             rx_err_r;
    reg             rx_err_1_r;
    
    

//*********************************Wire Declarations***************************
 
    wire            rx_er_c;
 
 
//*********************************Main Body of Code***************************



    //______________________ RGMII to GMII Conversion _________________________


    //Sample the least significant nibble of GMII data from the RGMII_RISING 
    // bus on the rising edge of the RGMII RX_CLK. The RGMII_RISING bus is the
    // data from the RGMII bus as seen by the Rising edge DDR Registers
    always @(posedge RX_CLK or posedge RESET)
        if(RESET)   rxd_r[3:0]  <=  4'h0;
        else        rxd_r[3:0]  <=  RGMII_RXD_RISING;
        

        
    //Sample the most significant nibble of GMII data from the RGMII_FALLING
    // bus on the falling edge of the RGMII RX_CLK. The RGMII_FALLING bus is
    // the data from the RGMII bus as seen by the Falling edge DDR Registers
    always @(negedge RX_CLK or posedge RESET)
        if(RESET)   rxd_r[7:4]  <=  4'h0;
        else        rxd_r[7:4]  <=  RGMII_RXD_FALLING;



    //Synchronize the GMII data from both edges to the GMII clock on the 
    // rising edge. Note that in this case we use the RGMII RX clock
    // as our GMII clock
    always @(posedge RX_CLK or posedge RESET)
        if(RESET)   rxd_1_r     <=  8'h00;
        else        rxd_1_r     <=  rxd_r;



    //Sample the Data Valid signal from the RGMII_RX_CTL_RISING line on the
    // rising edge of RX_CLK. RGMII_RX_CTL_RISING is the connection from
    // the positive edge DDR register connected to the RGMII_RX_CTL signal
    always @(posedge RX_CLK or posedge RESET) 
        if(RESET)   rx_dv_r     <=  1'b0;
        else        rx_dv_r     <=  RGMII_RX_CTL_RISING;
        
        
        
    //Sample the Data Valid signal from the RGMII_RX_CTL_FALLING line on the
    // falling edge of RX_CLK. RGMII_RX_CTL_FALLING is the connection from
    // the negative edge DDR register connected to the RGMII_RX_CTL signal
    always @(negedge RX_CLK or posedge RESET)
        if(RESET)   rx_err_r    <=  1'b0;
        else        rx_err_r    <=  RGMII_RX_CTL_FALLING;


  
    //Synchronize the GMII control signals from both edges to the GMII clock
    // on its Rising edge. In this design, the GMII clock is the RGMII RX
    // clock.
    always @(posedge RX_CLK or posedge RESET)
        if(RESET)
            begin
                    rx_dv_1_r   <=  1'b0;
                    rx_err_1_r  <=  1'b0;
            end
        else
            begin   
                    rx_dv_1_r   <=  rx_dv_r;
                    rx_err_1_r  <=  rx_err_r;
            end
            
                    

    //Decode the rx_er signal according to the RGMII spec
    assign  rx_er_c =   rx_err_1_r ^ rx_dv_1_r;



    //Register the output data 
    always @(posedge RX_CLK or posedge RESET)
        if(RESET)
            begin
                    GMII_RX_ER  <= 1'b0;
                    GMII_RX_DV  <= 1'b0;
                    GMII_RXD    <= 8'h00; 
            end
        else
            begin
                    GMII_RX_ER  <= rx_er_c;
                    GMII_RXD    <= rxd_1_r;
                    GMII_RX_DV  <= rx_dv_1_r;
            end
            
            
 
    //________________________ Indicator Signals___________________________
 
 
 
    //Indicate when data is being received through RGMII layers.
    // To be used by medium access control protocol during half-duplex
    always @(posedge RX_CLK or posedge RESET)
        if(RESET)                       RECEIVING   <=  1'b0;
        else if(rx_dv_1_r)              RECEIVING   <=  1'b1;
        else if(!rx_dv_1_r & !rx_er_c)  RECEIVING   <=  1'b0;
        
        
    
    //Extract optional RGMII status information from Inter Packet Gap
    always @(posedge RX_CLK or posedge RESET)
        if(RESET)
            begin
                    RGMII_RX_SPEED      <=  2'b00;
                    RGMII_RX_DUPLEX     <=  1'b0;
                    RGMII_LINK          <=  1'b0;
            end
        else if(!rx_dv_1_r & !rx_err_1_r)
            begin
                    RGMII_RX_SPEED      <=  rxd_1_r[2:1];
                    RGMII_RX_DUPLEX     <=  rxd_1_r[3];
                    RGMII_LINK          <=  rxd_1_r[0];
            end
  

endmodule