mac_address_swap.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

///////////////////////////////////////////////////////////////////////////////
//
//      Project:  RGMII/Gigabit Ethernet MAC
//      Version:  1.0
//      File   :  mac_address_swap.v
//
//      Company:  Xilinx
// Contributors:  Mary Low
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// MAC Address Swap Logic
// Author: Mary Low
//
// Description: This circuit switches the Source and Destination
//		MAC address of the incoming packet.  This is useful
//		for echoeing the packet that is received from the 
//		MAC and then transmit it back.  The ethernet packet
//    		has the following format:
//		 ____________  ____________  ____  _____...
//		/    SA1     \/	    DA1    \/T/L \/DATA
//	        \____________/\____________/\____/\_____... 
//
//		When the packet goes to this module, it will output
//        	the following:
//		 ____________  ____________  ____  _____...
//		/    SA2     \/	    DA2    \/T/L \/DATA
//	        \____________/\____________/\____/\_____... 
//
//		where SA1 = DA2 and DA1 = SA2.  This will add a delay
//		of six clock cyles to the data.  The received control 
//		signals RX_DATA_VALID, RX_GOOD_FRAME, and RX_BAD_FRAME 
//		will also be delayed for six clock cycles as well.
//               
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1 ps

module MAC_ADDRESS_SWAP 
(
    // RX Data In
    DATA_IN,        	
    DATA_VALID_IN,  	
    GOOD_FRAME_IN,  	
    BAD_FRAME_IN,   	
    
    // RX Data Out
    DATA_OUT,       	
    DATA_VALID_OUT, 	
    GOOD_FRAME_OUT, 	
    BAD_FRAME_OUT,  	

    // RX Clock
    CLK            	
);  


//*****************************Parameter Declarations**************************

    parameter	TDLY = 2; 


//***********************************Port Declarations*************************

    // RX Data In
    input  [7:0]	DATA_IN;       	// RX_DATA[7:0] signals from MAC
    input 	        DATA_VALID_IN; 	// RX_DATA_VALID signal from MAC
    input	        GOOD_FRAME_IN; 	// RX_GOOD_FRAME signal from MAC
    input	        BAD_FRAME_IN;  	// RX_BAD_FRAME signal from MAC
    
    
    // RX Data Out
    output [7:0]        DATA_OUT;      	// Data out with dst addr and src 
    				        // addr swapped to client
    output	        DATA_VALID_OUT;	// Delayed data valid signal to client
    output	        GOOD_FRAME_OUT;	// Delayed RX_GOOD_FRAME signal to 
    					// client
    output	        BAD_FRAME_OUT; 	// Delayed RX_BAD_FRAME signal to 
    					// client


    // RX Clock
    input	CLK;           	// Data clock


//*************************Internal Register Declarations**********************

    reg  [12:0]	        data_sel_cnt_r;


//*********************************Wire Declarations***************************

    wire [7:0]	        data_delay_i;
    wire	        data_valid_delay_i;
    wire	        good_frame_delay_i;
    wire	        bad_frame_delay_i;  

    wire [7:0]          data_delay_i2;
    wire 	        data_valid_delay_i2;
    wire 	        good_frame_delay_i2;
    wire 	        bad_frame_delay_i2;
 
    wire 	        data_sel_i;
    wire [7:0]          data_in_i;
    wire	        data_valid_in_i;
    wire 	        good_frame_in_i;
    wire 	        bad_frame_in_i;
 
    wire 	        data_delay_en_c;
    wire 	        data_sel_cnt_en_c;


//*********************************Main Body of Code***************************

    //__________________Delay the RX data and control signals__________________
    
    // RX DATA  
    SRL16E srl16e_data_0
    (
        .Q(data_delay_i[0]),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE (data_delay_en_c),
        .CLK(CLK),
        .D(data_in_i[0])
    );

    SRL16E srl16e_data_1
    (
        .Q(data_delay_i[1]),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE (data_delay_en_c),
        .CLK(CLK),
        .D(data_in_i[1])
    );
    
    SRL16E srl16e_data_2
    (
        .Q(data_delay_i[2]),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE (data_delay_en_c),
        .CLK(CLK),
        .D(data_in_i[2])
    );
    
    SRL16E srl16e_data_3
    (
        .Q(data_delay_i[3]),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE (data_delay_en_c),
        .CLK(CLK),
        .D(data_in_i[3])
    );
    
    SRL16E srl16e_data_4
    (
        .Q(data_delay_i[4]),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE (data_delay_en_c),
        .CLK(CLK),
        .D(data_in_i[4])
    );
    
    SRL16E srl16e_data_5
    (
        .Q(data_delay_i[5]),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE (data_delay_en_c),
        .CLK(CLK),
        .D(data_in_i[5])
    );
    
    SRL16E srl16e_data_6
    (
        .Q(data_delay_i[6]),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE (data_delay_en_c),
        .CLK(CLK),
        .D(data_in_i[6])
    );
    
    SRL16E srl16e_data_7
    (
        .Q(data_delay_i[7]),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE (data_delay_en_c),
        .CLK(CLK),
        .D(data_in_i[7])
    );
    

    // RX_DATA_VALID
    SRL16 srl16_data_valid
    (
        .Q(data_valid_delay_i),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CLK(CLK),
        .D(data_valid_in_i)
    );
    
    // RX_GOOD_FRAME
    SRL16 srl16_good_frame
    (
        .Q(good_frame_delay_i),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CLK(CLK),
        .D(good_frame_in_i)
    );      

    // RX_BAD_FRAME
    SRL16 srl16_bad_frame
    (
        .Q(bad_frame_delay_i),
        .A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CLK(CLK),
        .D(bad_frame_in_i)
    );      



    //_____________Assign delay to the signals for RTL simulation______________
    assign #TDLY data_in_i           = DATA_IN;
    assign #TDLY data_valid_in_i     = DATA_VALID_IN;
    assign #TDLY good_frame_in_i     = GOOD_FRAME_IN;
    assign #TDLY bad_frame_in_i      = BAD_FRAME_IN;
    assign #TDLY data_delay_i2       = data_delay_i;
    assign #TDLY data_valid_delay_i2 = data_valid_delay_i;
    assign #TDLY good_frame_delay_i2 = good_frame_delay_i;
    assign #TDLY bad_frame_delay_i2  = bad_frame_delay_i;


    //____________________Generate the control signals_________________________
    
    // One-hot counter that generates the signal to select the mux 
    // that chooses to write the data in or the delayed data in 
    // to the data out registers
    always@(posedge CLK)
        if(!data_valid_in_i & !data_valid_delay_i)
            data_sel_cnt_r[12:0] <= #TDLY 13'b1000000000000;
        else if(data_sel_cnt_en_c)
            data_sel_cnt_r <= #TDLY {data_sel_cnt_r[0], data_sel_cnt_r[12:1]};
    
    assign #TDLY data_sel_cnt_en_c = !data_sel_cnt_r[0] & DATA_VALID_IN; 
    assign data_sel_i        = data_sel_cnt_r[0];


    // This signal disables the SRL16 so that the dst addr can be
    // put in the right field
    assign data_delay_en_c = data_sel_i | !data_valid_delay_i;


    // MUX to select the streaming data coming in or a delayed version of it
    assign DATA_OUT = data_sel_i?data_delay_i:DATA_IN;
   
    // Assign the delayed control signals to output ports of the component
    assign DATA_VALID_OUT = data_valid_delay_i;
    assign GOOD_FRAME_OUT = good_frame_delay_i;
    assign BAD_FRAME_OUT  = bad_frame_delay_i;

endmodule