gmac_rgmii_echo.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );
    
    FDDRRSE rgmii_txd3_ddr
    (
        .Q(rgmii_txd_obuf[3]),
        .D0(rgmii_txd_rising_int[3]),
        .D1(rgmii_txd_falling_int[3]),
        .C0(rgmii_tx_clk_int),
        .C1(not_rgmii_tx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );


    // Transmit control DDR    
    FDDRRSE rgmii_tx_ctl_ddr
    (
        .Q(rgmii_tx_ctl_obuf),
        .D0(rgmii_tx_ctl_rising_int),
        .D1(rgmii_tx_ctl_falling_int),
        .C0(rgmii_tx_clk_int),
        .C1(not_rgmii_tx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );    

    ///////////////////////////////////////////////////////////////////////////
    // Instantiate OBUFs for Transmit signals 
    ///////////////////////////////////////////////////////////////////////////
    OBUF drive_rgmii_txd0   (.I(rgmii_txd_obuf[0]), .O(RGMII_TXD[0]));
    OBUF drive_rgmii_txd1   (.I(rgmii_txd_obuf[1]), .O(RGMII_TXD[1]));
    OBUF drive_rgmii_txd2   (.I(rgmii_txd_obuf[2]), .O(RGMII_TXD[2]));
    OBUF drive_rgmii_txd3   (.I(rgmii_txd_obuf[3]), .O(RGMII_TXD[3]));    
    
    OBUF drive_rgmii_tx_ctl (.I(rgmii_tx_ctl_obuf), .O(RGMII_TX_CTL));
 
    // TXD[7:4] of the PHY need to be driven LOW since they are not in use
    OBUF drive_rgmii_txd4   (.I(1'b0),  .O(RGMII_TXD[4]));
    OBUF drive_rgmii_txd5   (.I(1'b0),  .O(RGMII_TXD[5]));
    OBUF drive_rgmii_txd6   (.I(1'b0),  .O(RGMII_TXD[6]));
    OBUF drive_rgmii_txd7   (.I(1'b0),  .O(RGMII_TXD[7])); 
    
    
    ///////////////////////////////////////////////////////////////////////////
    // RGMII Receiver Clock Management: Use DCM to drive the RGMII_RX_CLK from 
    // the PHY
    ///////////////////////////////////////////////////////////////////////////
    IBUF ibuf_rgmii_rx_clk (.I(RGMII_RX_CLK),  .O(rgmii_rx_clk_ibuf));

    DCM dcm_rx_clk
    (
         .CLK0(rgmii_rx_clk_out), 
         .CLK180(), 
         .CLK270(rgmii_rx_clk270_out), 
         .CLK2X(), 
         .CLK2X180(), 
         .CLK90(rgmii_rx_clk90_out), 
         .CLKDV(), 
         .CLKFX(), 
         .CLKFX180(), 
         .LOCKED(dcm2_locked), 
         .PSDONE(), 
         .STATUS(), 
         .CLKFB(rgmii_rx_clk_bufg), 
         .CLKIN(rgmii_rx_clk_ibuf), 
         .DSSEN(1'b0), 
         .PSCLK(1'b0), 
         .PSEN(1'b0), 
         .PSINCDEC(1'b0), 
         .RST(1'b0) 
    ); 
    // synthesis attribute DLL_FREQUENCY_MODE of dcm_rx_clk is "LOW"
    // synthesis attribute CLKIN_PERIOD of dcm_rx_clk is "8"

    BUFG bufg_rx_clk    (.I(rgmii_rx_clk_out),    .O(rgmii_rx_clk_bufg));
  
    BUFG bufg_rx_clk90  (.I(rgmii_rx_clk90_out),  .O(rgmii_rx_clk90_bufg));

    BUFG bufg_rx_clk270 (.I(rgmii_rx_clk270_out), .O(rgmii_rx_clk270_bufg));

    // Use CLK270 of the DCM port to do the inversion clock that goes to 
    // IFDDRRSE.  
    assign not_rgmii_rx_clk_int = rgmii_rx_clk270_bufg;

    // 2 ns delay between RXD and RX_CLK according to the HP RGMII v2.0
    // specifications
    assign rgmii_rx_clk_int = rgmii_rx_clk90_bufg;

    ///////////////////////////////////////////////////////////////////////////
    // RGMII Receiver Logic :   Use Input DDR Flip-Flops to clock the RX data 
    // coming from the PHY
    ///////////////////////////////////////////////////////////////////////////
    // Receive data DDRs
    IFDDRRSE rgmii_rxd0_ddr
    (
        .D(RGMII_RXD[0]),
        .Q0(rgmii_rxd_rising_int[0]),
        .Q1(rgmii_rxd_falling_int[0]),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );
    
    IFDDRRSE rgmii_rxd1_ddr
    (
        .D(RGMII_RXD[1]),
        .Q0(rgmii_rxd_rising_int[1]),
        .Q1(rgmii_rxd_falling_int[1]),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );
    
    IFDDRRSE rgmii_rxd2_ddr
    (
        .D(RGMII_RXD[2]),
        .Q0(rgmii_rxd_rising_int[2]),
        .Q1(rgmii_rxd_falling_int[2]),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );
    
    IFDDRRSE rgmii_rxd3_ddr
    (
        .D(RGMII_RXD[3]),
        .Q0(rgmii_rxd_rising_int[3]),
        .Q1(rgmii_rxd_falling_int[3]),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );


    // Transmit control DDR    
    IFDDRRSE rgmii_rx_ctl_ddr
    (
        .D(RGMII_RX_CTL),
        .Q0(rgmii_rx_ctl_rising_int),
        .Q1(rgmii_rx_ctl_falling_int),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );    


    ///////////////////////////////////////////////////////////////////////////
    // Instantiate the GMAC core
    ///////////////////////////////////////////////////////////////////////////
    GMAC_RGMII gmac_core  
    (
        // Reset Signal
        .RESET(reset_i),               
        
        // Client Receiver Interface
        .RX_CLK(RX_CLK),              
        .RX_GOOD_FRAME(rx_good_frame_in),       
        .RX_BAD_FRAME(rx_bad_frame_in),        
        .RX_DATA(rx_data_in),             
        .RX_DATA_VALID(rx_data_valid_in),       
        .RX_STATISTICS_VECTOR(),
        .RX_STATISTICS_VALID(),
        
        // Client transmitter interface
        .TX_CLK(TX_CLK),              
        .TX_DATA(tx_data_i),              
        .TX_DATA_VALID(tx_data_valid_i),       
        .TX_UNDERRUN(tx_underrun_i),         
        .TX_ACK(tx_ack_i),              
        .TX_RETRANSMIT(),       
        .TX_COLLISION(),        
        .TX_IFG_DELAY(8'b00000000),        
        .TX_STATISTICS_VECTOR(),
        .TX_STATISTICS_VALID(),
        
        // MAC control interface
        .PAUSE_REQ(pause_req_i),           
        .PAUSE_VAL(pause_val_i),
        
        // RGMII interface
        .GTX_CLK(gtx_clk_bufg),    
        .RGMII_TX_CTL_RISING(rgmii_tx_ctl_rising_int),          
        .RGMII_TX_CTL_FALLING(rgmii_tx_ctl_falling_int),
        .RGMII_TXD_RISING(rgmii_txd_rising_int),
        .RGMII_TXD_FALLING(rgmii_txd_falling_int),
        .RGMII_TX_CLK(rgmii_tx_clk_int),
        .RGMII_RX_CTL_RISING(rgmii_rx_ctl_rising_int),
        .RGMII_RX_CTL_FALLING(rgmii_rx_ctl_falling_int),
        .RGMII_RXD_RISING(rgmii_rxd_rising_int),
        .RGMII_RXD_FALLING(rgmii_rxd_falling_int),
        .RGMII_RX_CLK(rgmii_rx_clk_int),
        .RGMII_RX_SPEED(),     
        .RGMII_RX_DUPLEX(RGMII_RX_DUPLEX),     
        .RGMII_LINK(RGMII_LINK),
        
        // MDIO interface
        .MDIO_IN(1'b1),   
        .MDIO_OUT(),
        .MDIO_TRI(),
        .MDC(),
        
        // HOST interface
        .HOST_CLK(1'b0),     
        .HOST_OPCODE(2'b00),  
        .HOST_ADDR(10'b0000000000),    
        .HOST_WR_DATA(32'h00000000), 
        .HOST_REQ(1'b0),     
        .HOST_MIIM_SEL(1'b0),
        .HOST_RD_DATA(), 
        .HOST_MIIM_RDY()       							   
    );      						   
        
 
    ///////////////////////////////////////////////////////////////////////////
    // Instantiation of the 1 Gig Ethernet MAC FIFO Reference Design(GMAC_FIFO)
    ///////////////////////////////////////////////////////////////////////////    
    GMAC_FIFO one_gig_ethernet_mac_fifo
    (
        // Reset signal
        .RESET(reset_i),
        
        // MAC Transmitter Interface
        .TX_CLK(gtx_clk_bufg),
        .TX_ACK(tx_ack_i),
        .TX_DATA_VALID(tx_data_valid_i),
        .TX_DATA(tx_data_i),
        .TX_UNDERRUN(tx_underrun_i),
        
        // MAC Receiver Interface
        .RX_CLK(rgmii_rx_clk_int),
        .RX_DATA(rx_data_out),
        .RX_DATA_VALID(rx_data_valid_out),
        .RX_GOOD_FRAME(rx_good_frame_out),
        .RX_BAD_FRAME(rx_bad_frame_out),
        
        // MAC Flow Control Interface
        .PAUSE_REQ(pause_req_i),
        .PAUSE_VAL(pause_val_i),
        
        // Client interface
        .WrClk(rgmii_rx_clk_int),               						      
        .RdClk(rgmii_rx_clk_int),
        .RdEn(rden_i),             							     
        .RdAck(rdack_i),                							       
        .Underflow(underflow_i),                							 
        .RdData(rddata_i),                     				         
        .Empty(empty_i),       							       
        .AlmostEmpty(almostempty_i),							        
        .WrData(wrdata_i),         							    
        .WrEn(rdack_i),
        .WrAck(wrack_i),                							     
        .Overflow(overflow_i),                
        .Full(full_i),        
        .AlmostFull(almostfull_i),
        
        // Management Interface
        .HOST_CLK(host_clk_bufg),
        .HOST_ADDR(10'b0000000000),
        .HOST_RD_DATA(),
        .HOST_WR_DATA(32'h00000000),
        .HOST_RNW(1'b0)    
    );                                    


    ///////////////////////////////////////////////////////////////////////////
    // Instantiate the component that swaps the Destination and Source MAC 
    // Addresses
    ///////////////////////////////////////////////////////////////////////////
    MAC_ADDRESS_SWAP mac_address_swap_i
    (
        .DATA_IN(rx_data_in),   
        .DATA_VALID_IN(rx_data_valid_in), 
        .GOOD_FRAME_IN(rx_good_frame_in),
        .BAD_FRAME_IN(rx_bad_frame_in),
        .DATA_OUT(rx_data_out),
        .DATA_VALID_OUT(rx_data_valid_out),
        .GOOD_FRAME_OUT(rx_good_frame_out),
        .BAD_FRAME_OUT(rx_bad_frame_out),      
        .CLK(rgmii_rx_clk_int)
    );

    
    ///////////////////////////////////////////////////////////////////////////
    // Enable Read of the FIFO when it is not empty.  When bit 16 of RdData is 
    // HIGH, data is valid for RdData[7:0]; connect this wire to WrData
    ///////////////////////////////////////////////////////////////////////////
    assign rden_i = !empty_i;
    assign wrdata_i = rddata_i[16]?rddata_i[17:0]:18'b000000000000000000;

    ///////////////////////////////////////////////////////////////////////////
    // Instantiation of IBUFs/OBUFs for Resetting the GMAC core and the PHY
    ///////////////////////////////////////////////////////////////////////////
    IBUF reset_ibuf (.I(RESET), .O(reset_i));
    IBUF pbutton_reset_ibuf (.I(PBUTTON_RESET), .O(phy_reset));
    OBUF phy_reset_n_obuf (.I(phy_reset_inv) , .O(PHY_RESET_N));

    assign phy_reset_inv = !phy_reset;
  
    ///////////////////////////////////////////////////////////////////////////
    // Host Clock 
    //  Cannot remove the Host Clock even though it is not used in the design
    //  Some of the reset wires in the GMAC FIFO are generated from this 
    //  Host Clock
    ///////////////////////////////////////////////////////////////////////////
    IBUFG ibufg_host_clk (.I(HOST_CLK), .O(host_clk_ibufg));
    BUFG  bufg_host_clk (.I(host_clk_ibufg), .O(host_clk_bufg));
                                    
    ///////////////////////////////////////////////////////////////////////////
    // Instantiation of OBUFs driving these wires to LEDs
    ///////////////////////////////////////////////////////////////////////////
    OBUF rdack_obuf       (.I(rdack_i),       .O(RDACK));
    OBUF underflow_obuf   (.I(underflow_i),   .O(UNDERFLOW));
    OBUF empty_obuf       (.I(empty_i),       .O(EMPTY));    
    OBUF almostempty_obuf (.I(almostempty_i), .O(ALMOSTEMPTY));
    OBUF wrack_obuf       (.I(wrack_i),       .O(WRACK));
    OBUF overflow_obuf    (.I(overflow_i),    .O(OVERFLOW));
    OBUF full_obuf        (.I(full_i),        .O(FULL));
    OBUF almostfull_obuf  (.I(almostfull_i),  .O(ALMOSTFULL));    

endmodule