gmac_rgmii_echo.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

///////////////////////////////////////////////////////////////////////////////
//
//      Project:  RGMII/Gigabit Ethernet MAC
//      Version:  1.0
//      File   :  gmac_rgmii_echo.v
//
//      Company:  Xilinx
// Contributors:  Mary Low
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// RGMII Gigabit Ethernet MAC Echo 
// Author: Mary Low
//
// Description: This module is a an echo design that uses the RGMII
//		One-Gigabit Ethernet MAC module (GMAC_RGMII), the
//		MAC Address Swap module, and the One-Gigabit FIFO
//		Reference Design (GMAC_FIFO).  This is illustrated  
//              below.
//
//
//      ---------------------------------------------------------------
//      |                 GMAC RGMII ECHO                             |
//	|		               ------------------------------ |
//      |    ----------                |  ----------    ----------  | |
//      |    |        |                |  |        |    |        |  | |TX
//    ->|--->|        |----------------|->|        |--->|        |--|-|->
//   |  |    |        |                |  |  GMAC  |    |        |  | | RGMII  
//   |  |    |  GMAC  |                |  |  Core  |    |  RGMII |  | | I/F      
//   |  |    |  FIFO  |    ----------  |  |  v3.0  |    |  Shim  |  | | to
//   |  |    |        |    |  MAC   |  |  |        |    |        |  | | PHY
//    <-|----|        |<---| Address|<-|--|        |<---|        |<-|-|--
//      |    |        |    |  Swap  |  |  |        |    |        |  | |RX
//      |    ----------    ----------  |  ----------    ----------  | |
//      |                              |         GMAC_RGMII         | |
//	|		               ------------------------------ |
//	|						              |
//      ---------------------------------------------------------------
//                       
//		Functionality:
//		1.  The GMAC_RGMII module combines the GMAC Core 
//		    version 3.0 and the RGMII Shim.  The GMAC Core
//		    is generated with MDIO interface.  The RGMII 
//		    wires are then connected to the respective 
//		    wires of the RGMII-mode PHY.
//		2.  The MAC Address Swap module takes the Ethernet
//		    packet from the MAC, swapping the source and
// 		    destination MAC address.  Once this packet is 
//		    processed, it goes to the GMAC FIFO.
//		3.  The GMAC FIFO takes the received data and echoes
//		    it back to the transmit side of the MAC, 
//		    transmitting the packet back to the PHY.
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1 ps	            
																					            
module GMAC_ECHO
(
    // Reset signal
    RESET,  
    
    // RGMII Interface
    RGMII_TXD,		
    RGMII_TX_CTL, 
    RGMII_TX_CLK, 
    RGMII_RXD,    
    RGMII_RX_CTL, 
    RGMII_RX_CLK, 
    
    // Host Interface
    HOST_CLK,  
    
    // Client Interface 
    RDACK, 	    	  
    UNDERFLOW,	    	      
    EMPTY,	    	 
    ALMOSTEMPTY,     	         
    WRACK,           	
    OVERFLOW,        	
    FULL,            	
    ALMOSTFULL,      	
  
    // Clock
    CLK_DIFF_P,		
    CLK_DIFF_N,		

    // PHY reset signals
    PBUTTON_RESET,
    PHY_RESET_N		
);/* synthesis syn_noclockbuf = 1 */

//*****************************Parameter Declarations**************************
    
    parameter C_TX_FIFO_DEPTH 	= 1024;
    parameter C_RX_FIFO_DEPTH	= 1024;
    
    parameter TDLY = 2;

//***********************************Port Declarations*************************

    // Reset signal
    input         RESET;  
    
    // RGMII Interface
    output [7:0]  RGMII_TXD;	// Tie RGMII_TXD[7:4] to ground
    output        RGMII_TX_CTL; 
    output        RGMII_TX_CLK;
    input  [3:0]  RGMII_RXD;    
    input         RGMII_RX_CTL; 
    input         RGMII_RX_CLK;
    
    // Host Interface
    input         HOST_CLK;
    
    // Client Interface - These wires go to LEDs of the ML320 board
    output        RDACK; 	// Data was successfully read from RX_FIFO        
    output        UNDERFLOW;	// Data was not successfully read from RX_FIFO        
    output        EMPTY;	// Status indicator that RX_FIFO is empty        
    output        ALMOSTEMPTY;  // Status indicator that RX_FIFO is almost emp.         
    output        WRACK;        // Data was successfully written to TX_FIFO
    output        OVERFLOW;     // Data was not successfully written to TX_FIFO
    output        FULL;         // Status indicator that TX_FIFO is full
    output        ALMOSTFULL;   // Status indicator that TX_FIFO is almost full
  
    // Clock
    input 	  CLK_DIFF_P;	// 125 MHz input differential clock
    input         CLK_DIFF_N;	// 125 MHz input differential clock

    // PHY reset wires
    input         PBUTTON_RESET;
    output        PHY_RESET_N;	// Active low reset the PHY

//*********************************Wire Declarations***************************

    // Reset signal
    wire          reset_i;
    
    // Signals for the MAC address swap module
    wire [7:0]	  rx_data_in;
    wire 	  rx_data_valid_in;
    wire 	  rx_good_frame_in;
    wire 	  rx_bad_frame_in;
    wire [7:0]	  rx_data_out;
    wire 	  rx_data_valid_out;
    wire 	  rx_good_frame_out;
    wire 	  rx_bad_frame_out;

    // GTX CLK signals
    wire 	  gtx_clk_ibufg;
    wire 	  gtx_clk_bufg;
 
    // RGMII TX clock signals
    wire 	  rgmii_tx_clk_int;
    wire 	  not_rgmii_tx_clk_int;
    wire 	  rgmii_tx_clk_obuf;   
    wire 	  rgmii_tx_clk90_out;
    wire 	  rgmii_tx_clk90_bufg;
    wire          rgmii_tx_clk180_out;
    wire          rgmii_tx_clk180_bufg;
    wire 	  rgmii_tx_clk_out;
    wire 	  rgmii_tx_clk_bufg;

    // RGMII RX clock signals     
    wire 	  rgmii_rx_clk_out;
    wire 	  rgmii_rx_clk_bufg;
    wire 	  rgmii_rx_clk_ibuf;
    wire 	  rgmii_rx_clk90_out;
    wire 	  rgmii_rx_clk90_bufg;
    wire          rgmii_rx_clk270_out;
    wire          rgmii_rx_clk270_bufg;
    wire 	  rgmii_rx_clk_int;
    wire 	  not_rgmii_rx_clk_int;

    // DCM signals	
    wire 	  dcm1_locked;
    wire 	  dcm2_locked;

    // RGMII TX signals
    wire 	  rgmii_tx_ctl_rising_int;
    wire 	  rgmii_tx_ctl_falling_int;
    wire [3:0]	  rgmii_txd_rising_int;
    wire [3:0]	  rgmii_txd_falling_int;
    wire 	  rgmii_tx_ctl_obuf;
    wire [3:0]    rgmii_txd_obuf;
    wire 	  rgmii_rx_ctl_rising_int;
    wire 	  rgmii_rx_ctl_falling_int;
    wire [3:0]	  rgmii_rxd_rising_int;
    wire [3:0]	  rgmii_rxd_falling_int;   
  
    // Host Clock signals         	  
    wire 	  host_clk_ibufg;
    wire 	  host_clk_bufg;
    
    // Client interface signals
    wire          rden_i;       	  
    wire          rdack_i;
    wire          underflow_i;	 	  
    wire          empty_i; 		  
    wire 	  almostempty_i; 	  
    wire 	  wrack_i;  
    wire [17:0]	  wrdata_i;
    wire [23:0]   rddata_i;
    wire          overflow_i;	  
    wire          full_i;	  
    wire          almostfull_i;
    
    wire [7:0]	  tx_data_i;
    wire	  tx_data_valid_i;
    wire	  tx_underrun_i;
    wire	  tx_ack_i;
    
    wire	  pause_req_i;
    wire [15:0]	  pause_val_i;
    
    // PHY reset signals
    wire 	  phy_reset;
    wire 	  phy_reset_inv;

//*********************************Main Body of Code***************************

    ///////////////////////////////////////////////////////////////////////////
    // GTX_CLK Clock Management
    ///////////////////////////////////////////////////////////////////////////   
    // The clock used for GTX_CLK is a 125 MHz differential oscillator from the 
    // ML320 board
    IBUFGDS_LVDS_25 ibufg_gtx_clk 
    (
        .I(CLK_DIFF_P),
        .IB(CLK_DIFF_N),
        .O(gtx_clk_ibufg)
    );
    
    BUFG bufg_gtx_clk (.I(gtx_clk_ibufg),     .O(gtx_clk_bufg));

    ////////////////////////////////////////////////////////////////////////////
    // RGMII Transmitter Clock Management: Use DCM to drive the RGMII_TX_CLK 
    // to PHY
    ////////////////////////////////////////////////////////////////////////////   
    DCM dcm_tx_clk
    (
         .CLK0(rgmii_tx_clk_out), 
         .CLK180(rgmii_tx_clk180_out), 
         .CLK270(), 
         .CLK2X(), 
         .CLK2X180(), 
         .CLK90(rgmii_tx_clk90_out), 
         .CLKDV(), 
         .CLKFX(), 
         .CLKFX180(), 
         .LOCKED(dcm1_locked), 
         .PSDONE(), 
         .STATUS(), 
         .CLKFB(rgmii_tx_clk_bufg), 
         .CLKIN(rgmii_tx_clk_int), 
         .DSSEN(1'b0), 
         .PSCLK(1'b0), 
         .PSEN(1'b0), 
         .PSINCDEC(1'b0), 
         .RST(1'b0) 
    ); 
    // synthesis attribute DLL_FREQUENCY_MODE of dcm_tx_clk is "LOW"
    // synthesis attribute CLKIN_PERIOD of dcm_tx_clk is "8"

    BUFG bufg_tx_clk    (.I(rgmii_tx_clk_out),    .O(rgmii_tx_clk_bufg));
  
    BUFG bufg_tx_clk90  (.I(rgmii_tx_clk90_out),  .O(rgmii_tx_clk90_bufg));

    BUFG bufg_tx_clk180 (.I(rgmii_tx_clk180_out), .O(rgmii_tx_clk180_bufg));

    // Use CLK180 of the DCM port to do the inversion clock that goes to 
    // FDDRRSE.  
    assign not_rgmii_tx_clk_int = rgmii_tx_clk180_bufg;

    // 2 ns delay between TXD and TX_CLK according to the HP RGMII v2.0
    // specifications
    OBUF drive_rgmii_tx_clk (.I(rgmii_tx_clk90_bufg), .O(RGMII_TX_CLK));
  
    ///////////////////////////////////////////////////////////////////////////
    // RGMII Transmitter Logic:  Use DDR Flip-Flops to clock the TX data on 
    // both the positive edge and negative edge which is then transmitted to 
    // the PHY
    ///////////////////////////////////////////////////////////////////////////
    // Transmit data DDRs
    FDDRRSE rgmii_txd0_ddr
    (
        .Q(rgmii_txd_obuf[0]),
        .D0(rgmii_txd_rising_int[0]),
        .D1(rgmii_txd_falling_int[0]),
        .C0(rgmii_tx_clk_int),
        .C1(not_rgmii_tx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );
    
    FDDRRSE rgmii_txd1_ddr
    (
        .Q(rgmii_txd_obuf[1]),
        .D0(rgmii_txd_rising_int[1]),
        .D1(rgmii_txd_falling_int[1]),
        .C0(rgmii_tx_clk_int),
        .C1(not_rgmii_tx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );
    
    FDDRRSE rgmii_txd2_ddr
    (
        .Q(rgmii_txd_obuf[2]),
        .D0(rgmii_txd_rising_int[2]),
        .D1(rgmii_txd_falling_int[2]),
        .C0(rgmii_tx_clk_int),
        .C1(not_rgmii_tx_clk_int),