rx_blockram.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(2*2)+9:(2*2)+8]));
      
        RAMB16_S2_S2 RAM_SIZE521b
          (.DIA(DIA[(2*2)+1:(2*2)]),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(2*2)+1:(2*2)]));

        RAMB16_S2_S2 RAM_SIZE531
          (.DIA(DIA[(1*2)+9:(1*2)+8]),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(1*2)+9:(1*2)+8]));
      
        RAMB16_S2_S2 RAM_SIZE531b
          (.DIA(DIA[(1*2)+1:(1*2)]),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(1*2)+1:(1*2)]));

        RAMB16_S2_S2 RAM_SIZE541
          (.DIA(DIA[(0*2)+9:(0*2)+8]),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(0*2)+9:(0*2)+8]));
      
        RAMB16_S2_S2 RAM_SIZE541b
          (.DIA(DIA[(0*2)+1:(0*2)]),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(0*2)+1:(0*2)]));

        assign DV_IN7 = {1'b0, DIPA[1]};
           
        RAMB16_S2_S2 RAM_SIZE512
          (.DIA(DV_IN7),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RDV_TEMP7));
      
        assign DOPB[1] = RDV_TEMP7[0];
        assign DV_IN8 = {1'b0, DIPA[0]};

        RAMB16_S2_S2 RAM_SIZE512b
          (.DIA(DV_IN8),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RDV_TEMP8));
           
        assign DOPB[0] = RDV_TEMP8[0];

    */
    // (FIFO_SIZE == 16384)
    /*
        RAMB16_S1_S1 RAM_SIZE611
          (.DIA(DIA[7+8:7+8]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[7+8:7+8]));
      
        RAMB16_S1_S1 RAM_SIZE611b
          (.DIA(DIA[7:7]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[7:7]));
              
        RAMB16_S1_S1 RAM_SIZE621
          (.DIA(DIA[6+8:6+8]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[6+8:6+8]));
      
        RAMB16_S1_S1 RAM_SIZE621b
          (.DIA(DIA[6:6]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[6:6]));
              
        RAMB16_S1_S1 RAM_SIZE631
          (.DIA(DIA[5+8:5+8]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[5+8:5+8]));
      
        RAMB16_S1_S1 RAM_SIZE631b
          (.DIA(DIA[5:5]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[5:5]));
              
        RAMB16_S1_S1 RAM_SIZE641
          (.DIA(DIA[4+8:4+8]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[4+8:4+8]));
      
        RAMB16_S1_S1 RAM_SIZE641b
          (.DIA(DIA[4:4]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[4:4]));
             
        RAMB16_S1_S1 RAM_SIZE651
          (.DIA(DIA[3+8:3+8]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[3+8:3+8]));
      
        RAMB16_S1_S1 RAM_SIZE651b
          (.DIA(DIA[3:3]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[3:3]));
              
        RAMB16_S1_S1 RAM_SIZE661
          (.DIA(DIA[2+8:2+8]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[2+8:2+8]));
      
        RAMB16_S1_S1 RAM_SIZE661b
          (.DIA(DIA[2:2]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[2:2]));
              
        RAMB16_S1_S1 RAM_SIZE671
          (.DIA(DIA[1+8:1+8]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[1+8:1+8]));
      
        RAMB16_S1_S1 RAM_SIZE671b
          (.DIA(DIA[1:1]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[1:1]));
              
        RAMB16_S1_S1 RAM_SIZE681
          (.DIA(DIA[0+8:0+8]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[0+8:0+8]));
      
        RAMB16_S1_S1 RAM_SIZE681b
          (.DIA(DIA[0:0]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[0:0]));
       
       
        RAMB16_S1_S1 RAM_SIZE612
          (.DIA(DIPA[1:1]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOPB[1:1]));
      
        RAMB16_S1_S1 RAM_SIZE612b
          (.DIA(DIPA[0:0]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOPB[0:0]));
      */
endmodule