rx_blockram.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

           .ADDRB(ADDRB),
           .DOB(RDV_TEMP7));
      
        assign DOPB[1] = RDV_TEMP7[0];
        assign DV_IN8 = {1'b0, DIPA[0]};

        RAMB16_S2_S2 RAM_SIZE512b
          (.DIA(DV_IN8),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RDV_TEMP8));
           
        assign DOPB[0] = RDV_TEMP8[0];
      end
      
      else if(FIFO_SIZE == 16384)
      begin
        generate
          for(i = 7; i >= 0; i = i - 1)
          begin
            RAMB16_S1_S1 RAM_SIZE611
              (.DIA(DIA[i+8:i+8]),
               .DIB(UNUSED_DATA[0:0]),
               .ENA(ENA_UPPER),
               .ENB(ENB_INT),
               .WEA(LOGIC1),
               .WEB(LOGIC0),
               .SSRA(LOGIC0),
               .SSRB(SSRB),
               .CLKA(CLKA),
               .CLKB(CLKB),
               .ADDRA(ADDRA),
               .ADDRB(ADDRB),
               .DOB(DOB[i+8:i+8]));
      
            RAMB16_S1_S1 RAM_SIZE611b
              (.DIA(DIA[i:i]),
               .DIB(UNUSED_DATA[0:0]),
               .ENA(ENA_LOWER),
               .ENB(ENB_INT),
               .WEA(LOGIC1),
               .WEB(LOGIC0),
               .SSRA(LOGIC0),
               .SSRB(SSRB),
               .CLKA(CLKA),
               .CLKB(CLKB),
               .ADDRA(ADDRA),
               .ADDRB(ADDRB),
               .DOB(DOB[i:i]));
          end
        endgenerate

        RAMB16_S1_S1 RAM_SIZE612
          (.DIA(DIPA[1:1]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOPB[1:1]));
      
        RAMB16_S1_S1 RAM_SIZE612b
          (.DIA(DIPA[0:0]),
           .DIB(UNUSED_DATA[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOPB[0:0]));
      end             
    endgenerate                      
    */

    // CHANGES REQUIRED
    // Use the code below when Verilog 2001 generate statements are NOT supported...
    // Uncomment the code for the correct FIFO_SIZE...
    // (FIFO_SIZE == 512) 
    /*
        assign DATA_IN1 = {24'h000000, DIA[15:8]};
        assign DV_IN1 = {3'b000, DIPA[1]};
                           
        RAMB16_S36_S36 RAM_SIZE111a 
          (.DIA(DATA_IN1),
           .DIB(UNUSED_DATA),
           .DIPA(DV_IN1),
           .DIPB(UNUSED_PARITY),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOA(),
           .DOPA(),
           .DOB(RD_TEMP1),
           .DOPB(RDV_TEMP1));
       
        assign DOB[15:8] = RD_TEMP1[7:0];
        assign DOPB[1] = RDV_TEMP1[0];

        assign DATA_IN2 = {24'h000000, DIA[7:0]};
        assign DV_IN2 = {3'b000, DIPA[0]};
      
        RAMB16_S36_S36 RAM_SIZE111b 
          (.DIA(DATA_IN2),        // Both Data bits and
           .DIB(UNUSED_DATA),     //
           .DIPA(DV_IN2),         // Data Parity bits are used for storage.
           .DIPB(UNUSED_PARITY),
           .ENA(ENA_LOWER),       // Lower 9 bits have separate Enable. 
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOA(),
           .DOPA(),
           .DOB(RD_TEMP2),
           .DOPB(RDV_TEMP2));
       
        assign DOB[7:0] = RD_TEMP2[7:0];
        assign DOPB[0] = RDV_TEMP2[0];
    */
    // (FIFO_SIZE == 1024)
    
        assign DATA_IN3 = {8'h00, DIA[15:8]};
        assign DV_IN3 = {1'b0, DIPA[1]};
      
        RAMB16_S18_S18 RAM_SIZE211
          (.DIA(DATA_IN3),
           .DIB(UNUSED_DATA[15:0]),
           .DIPA(DV_IN3),
           .DIPB(UNUSED_PARITY[1:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOA(),
           .DOPA(),
           .DOB(RD_TEMP3),
           .DOPB(RDV_TEMP3));

        assign DOB[15:8] = RD_TEMP3[7:0];
        assign DOPB[1] = RDV_TEMP3[0];

        assign DATA_IN4 = {8'h00, DIA[7:0]};
        assign DV_IN4 = {1'b0, DIPA[0]};
      
        RAMB16_S18_S18 RAM_SIZE211b
          (.DIA(DATA_IN4),
           .DIB(UNUSED_DATA[15:0]),
           .DIPA(DV_IN4),
           .DIPB(UNUSED_PARITY[1:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOA(),
           .DOPA(),
           .DOB(RD_TEMP4),
           .DOPB(RDV_TEMP4));


        assign DOB[7:0] = RD_TEMP4[7:0];
        assign DOPB[0] = RDV_TEMP4[0];
    

    // (FIFO_SIZE == 2048)
    /*
        RAMB16_S9_S9 RAM_SIZE311
          (.DIA(DIA[15:8]),
           .DIB(UNUSED_DATA[7:0]),
           .DIPA(DIPA[1:1]),
           .DIPB(UNUSED_PARITY[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOA(),
           .DOPA(),
           .DOB(DOB[15:8]),
           .DOPB(DOPB[1:1]));

        RAMB16_S9_S9 RAM_SIZE311b
          (.DIA(DIA[7:0]),
           .DIB(UNUSED_DATA[7:0]),
           .DIPA(DIPA[0:0]),
           .DIPB(UNUSED_PARITY[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOA(),
           .DOPA(),
           .DOB(DOB[7:0]),
           .DOPB(DOPB[0:0]));
    */

    // (FIFO_SIZE == 4096)
    /*
        RAMB16_S4_S4 RAM_SIZE411
          (.DIA(DIA[(1*4)+11:(1*4)+8]),
           .DIB(UNUSED_DATA[3:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(1*4)+11:(1*4)+8]));
      
        RAMB16_S4_S4 RAM_SIZE411b
          (.DIA(DIA[(1*4)+3:(1*4)]),
           .DIB(UNUSED_DATA[3:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(1*4)+3:(1*4)]));
           
        RAMB16_S4_S4 RAM_SIZE421
          (.DIA(DIA[(0*4)+11:(0*4)+8]),
           .DIB(UNUSED_DATA[3:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(0*4)+11:(0*4)+8]));
      
        RAMB16_S4_S4 RAM_SIZE421b
          (.DIA(DIA[(0*4)+3:(0*4)]),
           .DIB(UNUSED_DATA[3:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(0*4)+3:(0*4)]));

        assign DV_IN5 = {3'b000, DIPA[1]};
      
        RAMB16_S4_S4 RAM_SIZE412
          (.DIA(DV_IN5),
           .DIB(UNUSED_DATA[3:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RDV_TEMP5));
      
        assign DOPB[1] = RDV_TEMP5;
        assign DV_IN6 = {3'b000, DIPA[0]};

        RAMB16_S4_S4 RAM_SIZE412b
          (.DIA(DV_IN6),
           .DIB(UNUSED_DATA[3:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RDV_TEMP6));
           
        assign DOPB[0] = RDV_TEMP6[0];
    */

    // (FIFO_SIZE == 8192)
    /*
        RAMB16_S2_S2 RAM_SIZE511
          (.DIA(DIA[(3*2)+9:(3*2)+8]),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(3*2)+9:(3*2)+8]));
      
        RAMB16_S2_S2 RAM_SIZE511b
          (.DIA(DIA[(3*2)+1:(3*2)]),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[(3*2)+1:(3*2)]));

        RAMB16_S2_S2 RAM_SIZE521
          (.DIA(DIA[(2*2)+9:(2*2)+8]),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),