rx_blockram.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

///////////////////////////////////////////////////////////////////////////////
//
//      Project:  1 Gig Ethernet MAC FIFO Reference Design
//      Version:  2.0
//      File   :  rx_blockram.vhd
//
//      Company:  Xilinx
// Contributors:  Xilinx Inc.
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// Virtex2 BlockRAM Wrapper.
// Author: Xilinx Inc.
//
// Description:  This module creates a blockram wrapper, using as many 
//               individual block rams as are required to produce the Backend 
//               Receiver FIFO. 
// 
///////////////////////////////////////////////////////////////////////////////


`timescale 1 ps / 1 ps	

module RX_BLOCKRAM 
    (
      SSRB,			
      DIA,         
      DIPA,        
      ADDRA,       
      ENA_UPPER,   
      ENA_LOWER,   
      CLKA,        
									
      ADDRB,       
      ENB,                        
      CLKB,                          
									
      DOB,          
      DOPB              																						
    );

    // CHANGES REQUIRED
    parameter FIFO_SIZE = 1024; // Possible sizes are 512, 1024, 2048, 4096, 8192, 16384
    parameter log2_FIFO_SIZE = (FIFO_SIZE == 512 ? 9 : 
                                 (FIFO_SIZE == 1024 ? 10 :
                                   (FIFO_SIZE == 2048 ? 11 :
                                     (FIFO_SIZE == 4096 ? 12 :
                                       (FIFO_SIZE == 8192 ? 13 : 14)))));

    input SSRB;						  // Port B synchronous reset
    input [15:0] DIA;                 // Port A data input.   
    input [1:0] DIPA;                 // Port A parity input.      
    input [log2_FIFO_SIZE-1:0] ADDRA; // Port A Address.            
    input ENA_UPPER;                  // Port A upper word enable.            
    input ENA_LOWER;                  // Port A lower word enable.           
    input CLKA;                       // Port A clock.            
																						
    input [log2_FIFO_SIZE-1:0] ADDRB; // Port B Address.                
    input ENB;                        // Port B enable.                
    input CLKB;                       // Port B clock.                    
																						
    output [15:0] DOB;                // Port B data output.                   
    output [1:0] DOPB;                // Port B parity output.                    




    wire LOGIC1;                       // Logic 1 signal. 
    wire LOGIC0;                       // Logic 0 Signal. 
    wire [31:0] UNUSED_DATA;           // Unused Port B data input.  
    wire [3:0] UNUSED_PARITY;          // Unused Port B parity input.
    wire ENB_INT;					  // Port B enable combined with reset

    wire [31:0] DATA_IN1, DATA_IN2;
    wire [3:0] DV_IN1, DV_IN2;
    wire [31:0] RD_TEMP1, RD_TEMP2;
    wire [3:0] RDV_TEMP1, RDV_TEMP2;
   
    wire [15:0] DATA_IN3, DATA_IN4;
    wire [1:0] DV_IN3, DV_IN4;
    wire [15:0] RD_TEMP3, RD_TEMP4;
    wire [1:0] RDV_TEMP3, RDV_TEMP4;
   
    wire [3:0] DV_IN5, DV_IN6;
    wire [3:0] RDV_TEMP5, RDV_TEMP6;
    wire [1:0] DV_IN7, DV_IN8;
    wire [1:0] RDV_TEMP7, RDV_TEMP8;


    assign LOGIC1 = 1'b1;
    assign LOGIC0 = 1'b0;
    assign UNUSED_DATA = 0;
    assign UNUSED_PARITY = 0;
    assign ENB_INT = ENB | SSRB;

//-----------------------------------------------------------------------------------
//  THE FOLLOWING CODE USES BLOCK RAMs TO CREATE THE 18 * FIFO_SIZE WORD FIFO.     --
//  The Block RAMs used are configured as required.                                --
//-----------------------------------------------------------------------------------
                          
    // Use the code below when Verilog 2001 generate statements are supported....
    /*    
    generate
      if (FIFO_SIZE == 512) 
      begin
        assign DATA_IN1 = {24'h000000, DIA[15:0]};
        assign DV_IN1 = {3'b000, DIPA[1]};
                           
        RAMB16_S36_S36 RAM_SIZE111a 
          (.DIA(DATA_IN1),
           .DIB(UNUSED_DATA),
           .DIPA(DV_IN1),
           .DIPB(UNUSED_PARITY),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RD_TEMP1),
           .DOPB(RDV_TEMP1));
       
        assign DOB[15:8] = RD_TEMP1[7:0];
        assign DOPB[1] = RDV_TEMP1[0];

        assign DATA_IN2 = {24'h000000, DIA[7:0]};
        assign DV_IN2 = {3'b000, DIPA[0]};
      
        RAMB16_S36_S36 RAM_SIZE111b 
          (.DIA(DATA_IN2),        // Both Data bits and
           .DIB(UNUSED_DATA),     //
           .DIPA(DV_IN2),         // Data Parity bits are used for storage.
           .DIPB(UNUSED_PARITY),
           .ENA(ENA_LOWER),       // Lower 9 bits have separate Enable. 
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RD_TEMP2),
           .DOPB(RDV_TEMP2));
       
        assign DOB[7:0] = RD_TEMP2[7:0];
        assign DOPB[0] <= RDV_TEMP2[0];
      end
      
      else if(FIFO_SIZE == 1024)
      begin
        assign DATA_IN3 = {8'h00, DIA[15:8]};
        assign DV_IN3 = {1'b0, DIPA[1]};
      
        RAMB16_S18_S18 RAM_SIZE211
          (.DIA(DATA_IN3),
           .DIB(UNUSED_DATA[15:0]),
           .DIPA(DV_IN3),
           .DIPB(UNUSED_PARITY[1:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RD_TEMP3),
           .DOPB(RDV_TEMP3));

        assign DOB[15:8] = RD_TEMP3[7:0];
        assign DOPB[1] = RDV_TEMP3[0];

        assign DATA_IN4 = {8'h00, DIA[7:0]};
        assign DV_IN4 = {1'b0, DIPA[0]};
      
        RAMB16_S18_S18 RAM_SIZE211b
          (.DIA(DATA_IN4),
           .DIB(UNUSED_DATA[15:0]),
           .DIPA(DV_IN4),
           .DIPB(UNUSED_PARITY[1:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RD_TEMP4),
           .DOPB(RDV_TEMP4));


        assign DOB[7:0] = RD_TEMP4[7:0];
        assign DOPB[0] = RDV_TEMP4[0];
      end
      
      else if(FIFO_SIZE == 2048)
      begin
        RAMB16_S9_S9 RAM_SIZE311
          (.DIA(DIA[15:8]),
           .DIB(UNUSED_DATA[7:0]),
           .DIPA(DIPA[1:1]),
           .DIPB(UNUSED_PARITY[0:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[15:8]),
           .DOPB(DOPB[1:1]));

        RAMB16_S9_S9 RAM_SIZE311b
          (.DIA(DIA[7:0]),
           .DIB(UNUSED_DATA[7:0]),
           .DIPA(DIPA[0:0]),
           .DIPB(UNUSED_PARITY[0:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(DOB[7:0]),
           .DOPB(DOPB[0:0]));
      end
      
      else if(FIFO_SIZE == 4096)
      begin
        generate
          for(i = 1; i >= 0; i = i - 1)
          begin
            RAMB16_S4_S4 RAM_SIZE411
              (.DIA(DIA[(i*4)+11:(i*4)+8]),
               .DIB(UNUSED_DATA[3:0]),
               .ENA(ENA_UPPER),
               .ENB(ENB_INT),
               .WEA(LOGIC1),
               .WEB(LOGIC0),
               .SSRA(LOGIC0),
               .SSRB(SSRB),
               .CLKA(CLKA),
               .CLKB(CLKB),
               .ADDRA(ADDRA),
               .ADDRB(ADDRB),
               .DOB(DOB[(i*4)+11:(i*4)+8]));
      
            RAMB16_S4_S4 RAM_SIZE411b
              (.DIA(DIA[(i*4)+3:(i*4)]),
               .DIB(UNUSED_DATA[3:0]),
               .ENA(ENA_LOWER),
               .ENB(ENB_INT),
               .WEA(LOGIC1),
               .WEB(LOGIC0),
               .SSRA(LOGIC0),
               .SSRB(SSRB),
               .CLKA(CLKA),
               .CLKB(CLKB),
               .ADDRA(ADDRA),
               .ADDRB(ADDRB),
               .DOB(DOB[(i*4)+3:(i*4)]));
          end
        endgenerate
           
        assign DV_IN5 = {3'b000, DIPA[1]};
      
        RAMB16_S4_S4 RAM_SIZE412
          (.DIA(DV_IN5),
           .DIB(UNUSED_DATA[3:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RDV_TEMP5));
      
        assign DOPB[1] = RDV_TEMP5;
        assign DV_IN6 = {3'b000, DIPA[0]};

        RAMB16_S4_S4 RAM_SIZE412b
          (.DIA(DV_IN6),
           .DIB(UNUSED_DATA[3:0]),
           .ENA(ENA_LOWER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),
           .ADDRB(ADDRB),
           .DOB(RDV_TEMP6));
           
        assign DOPB[0] = RDV_TEMP6[0];
      end
      
      else if(FIFO_SIZE == 8192)
      begin
        generate
          for(i = 3; i >= 0; i = i - 1)
          begin
            RAMB16_S2_S2 RAM_SIZE511
              (.DIA(DIA[(i*2)+9:(i*2)+8]),
               .DIB(UNUSED_DATA[1:0]),
               .ENA(ENA_UPPER),
               .ENB(ENB_INT),
               .WEA(LOGIC1),
               .WEB(LOGIC0),
               .SSRA(LOGIC0),
               .SSRB(SSRB),
               .CLKA(CLKA),
               .CLKB(CLKB),
               .ADDRA(ADDRA),
               .ADDRB(ADDRB),
               .DOB(DOB[(i*2)+9:(i*2)+8]));
      
            RAMB16_S2_S2 RAM_SIZE511b
              (.DIA(DIA[(i*2)+1:(i*2)]),
               .DIB(UNUSED_DATA[1:0]),
               .ENA(ENA_LOWER),
               .ENB(ENB_INT),
               .WEA(LOGIC1),
               .WEB(LOGIC0),
               .SSRA(LOGIC0),
               .SSRB(SSRB),
               .CLKA(CLKA),
               .CLKB(CLKB),
               .ADDRA(ADDRA),
               .ADDRB(ADDRB),
               .DOB(DOB[(i*2)+1:(i*2)]));
          end
        endgenerate
        
        assign DV_IN7 = {1'b0, DIPA[1]};
           
        RAMB16_S2_S2 RAM_SIZE512
          (.DIA(DV_IN7),
           .DIB(UNUSED_DATA[1:0]),
           .ENA(ENA_UPPER),
           .ENB(ENB_INT),
           .WEA(LOGIC1),
           .WEB(LOGIC0),
           .SSRA(LOGIC0),
           .SSRB(SSRB),
           .CLKA(CLKA),
           .CLKB(CLKB),
           .ADDRA(ADDRA),