generic_receive_fifo.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

      for(i = log2_FIFO_SIZE-1; i >= 0; i = i - 1)
      begin
	    assign FULL_COMPARE[i] = (~(RD_LASTGRAY[i] ^ WR_ADDRGRAY[i]) & FULL) |
   				(~(RD_LASTGRAY[i] ^ WR_NEXTGRAY[i]) & (~FULL));
   	  end
    endgenerate
    */
    
    // CHANGES REQUIRED
    // Use the code below when Verilog 2001 generate statements are NOT supported...
    // Uncomment the code for the correct FIFO_SIZE...
    // (FIFO_SIZE >= 512)     
    assign FULL_COMPARE[0] = (~(RD_LASTGRAY[0] ^ WR_ADDRGRAY[0]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[0] ^ WR_NEXTGRAY[0]) & ~FULL); // write pointer = read pointer - 1

    assign FULL_COMPARE[1] = (~(RD_LASTGRAY[1] ^ WR_ADDRGRAY[1]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[1] ^ WR_NEXTGRAY[1]) & ~FULL); // write pointer = read pointer - 1

    assign FULL_COMPARE[2] = (~(RD_LASTGRAY[2] ^ WR_ADDRGRAY[2]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[2] ^ WR_NEXTGRAY[2]) & ~FULL); // write pointer = read pointer - 1

    assign FULL_COMPARE[3] = (~(RD_LASTGRAY[3] ^ WR_ADDRGRAY[3]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[3] ^ WR_NEXTGRAY[3]) & ~FULL); // write pointer = read pointer - 1

    assign FULL_COMPARE[4] = (~(RD_LASTGRAY[4] ^ WR_ADDRGRAY[4]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[4] ^ WR_NEXTGRAY[4]) & ~FULL); // write pointer = read pointer - 1

    assign FULL_COMPARE[5] = (~(RD_LASTGRAY[5] ^ WR_ADDRGRAY[5]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[5] ^ WR_NEXTGRAY[5]) & ~FULL); // write pointer = read pointer - 1

    assign FULL_COMPARE[6] = (~(RD_LASTGRAY[6] ^ WR_ADDRGRAY[6]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[6] ^ WR_NEXTGRAY[6]) & ~FULL); // write pointer = read pointer - 1

    assign FULL_COMPARE[7] = (~(RD_LASTGRAY[7] ^ WR_ADDRGRAY[7]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[7] ^ WR_NEXTGRAY[7]) & ~FULL); // write pointer = read pointer - 1

    assign FULL_COMPARE[8] = (~(RD_LASTGRAY[8] ^ WR_ADDRGRAY[8]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[8] ^ WR_NEXTGRAY[8]) & ~FULL); // write pointer = read pointer - 1

    // (FIFO_SIZE >= 1024) Use this line also
    assign FULL_COMPARE[9] = (~(RD_LASTGRAY[9] ^ WR_ADDRGRAY[9]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[9] ^ WR_NEXTGRAY[9]) & ~FULL); // write pointer = read pointer - 1

    // (FIFO_SIZE >= 2048) Use this line also
    /*
    assign FULL_COMPARE[10] = (~(RD_LASTGRAY[10] ^ WR_ADDRGRAY[10]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[10] ^ WR_NEXTGRAY[10]) & ~FULL); // write pointer = read pointer - 1
    */
    // (FIFO_SIZE >= 4096) Use this line also
    /*
    assign FULL_COMPARE[11] = (~(RD_LASTGRAY[11] ^ WR_ADDRGRAY[11]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[11] ^ WR_NEXTGRAY[11]) & ~FULL); // write pointer = read pointer - 1
    */
    // (FIFO_SIZE >= 8192) Use this line also
    /*
    assign FULL_COMPARE[12] = (~(RD_LASTGRAY[12] ^ WR_ADDRGRAY[12]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[12] ^ WR_NEXTGRAY[12]) & ~FULL); // write pointer = read pointer - 1
    */
    // (FIFO_SIZE == 16384) Use this line also
    /*
    assign FULL_COMPARE[13] = (~(RD_LASTGRAY[13] ^ WR_ADDRGRAY[13]) & FULL) |   // write pointer = read pointer
                  (~(RD_LASTGRAY[13] ^ WR_NEXTGRAY[13]) & ~FULL); // write pointer = read pointer - 1
    */
    MUXCY_L FMUXCY0
	  (.DI(LOGIC0),
	   .CI(LOGIC1),       
	   .S(FULL_COMPARE[0]),
	   .LO(FULL_MUXCYO[0]));

    // Use the code below when Verilog 2001 generate statements are supported....
    /*    
    generate
      for(i = COUNT_WIDTH-1; i >= 1; i = i - 1)
      begin
        MUXCY_L FMUXCY 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[i-1]),
          .S(FULL_COMPARE[i]),
          .LO(FULL_MUXCYO[i]));
      end
    endgenerate
    */
    
    // CHANGES REQUIRED
    // Use the code below when Verilog 2001 generate statements are NOT supported...
    // Uncomment the code for the correct FIFO_SIZE...
    // (FIFO_SIZE >= 512)     
    MUXCY_L FMUXCY1 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[1-1]),
          .S(FULL_COMPARE[1]),
          .LO(FULL_MUXCYO[1]));

    MUXCY_L FMUXCY2 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[2-1]),
          .S(FULL_COMPARE[2]),
          .LO(FULL_MUXCYO[2]));

    MUXCY_L FMUXCY3 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[3-1]),
          .S(FULL_COMPARE[3]),
          .LO(FULL_MUXCYO[3]));

    MUXCY_L FMUXCY4 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[4-1]),
          .S(FULL_COMPARE[4]),
          .LO(FULL_MUXCYO[4]));

    MUXCY_L FMUXCY5 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[5-1]),
          .S(FULL_COMPARE[5]),
          .LO(FULL_MUXCYO[5]));

    MUXCY_L FMUXCY6 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[6-1]),
          .S(FULL_COMPARE[6]),
          .LO(FULL_MUXCYO[6]));

    MUXCY_L FMUXCY7 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[7-1]),
          .S(FULL_COMPARE[7]),
          .LO(FULL_MUXCYO[7]));

    MUXCY_L FMUXCY8 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[8-1]),
          .S(FULL_COMPARE[8]),
          .LO(FULL_MUXCYO[8]));

    // (FIFO_SIZE >= 1024) Use this line also
    MUXCY_L FMUXCY9 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[9-1]),
          .S(FULL_COMPARE[9]),
          .LO(FULL_MUXCYO[9]));

    // (FIFO_SIZE >= 2048) Use this line also
    /*
    MUXCY_L FMUXCY10 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[10-1]),
          .S(FULL_COMPARE[10]),
          .LO(FULL_MUXCYO[10]));
    */
    // (FIFO_SIZE >= 4096) Use this line also
    /*
    MUXCY_L FMUXCY11 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[11-1]),
          .S(FULL_COMPARE[11]),
          .LO(FULL_MUXCYO[11]));
    */
    // (FIFO_SIZE >= 8192) Use this line also
    /*
    MUXCY_L FMUXCY12 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[12-1]),
          .S(FULL_COMPARE[12]),
          .LO(FULL_MUXCYO[12]));
    */
    // (FIFO_SIZE == 16384) Use this line also
    /*
    MUXCY_L FMUXCY13 
         (.DI(LOGIC0),
          .CI(FULL_MUXCYO[13-1]),
          .S(FULL_COMPARE[13]),
          .LO(FULL_MUXCYO[13]));
    */

// purpose: Produce FULL signal, having had compared write and read gray code pointers. 
// type   : sequential
    always @(posedge RX_CLK)
    begin
      if(RX_SRESET == 1'b1)
        FULL     <= 1'b0;
      else if ((FULL | WR_UPPER) == 1'b1)
        FULL  <= FULL_MUXCYO[log2_FIFO_SIZE-1] |               // use final output of carry chain to set                       
                   (FULL & RX_DATA_VALID_REG1);                // keep full high until end of frame.                             
    end 



// purpose: Reclock Full flag from RX_CLK to FIFO_CLK. Full is accurate on the RX_CLK.  It is not 
//          therefore (and does not need to be) completely accurate on the RX_FIFO_CLK.
// type   : sequential
    always @(posedge FIFO_CLK)
    begin
      if(RX_FIFO_SRESET == 1'b1)
        STATUS_FULL          <= 1'b0;
      else
        STATUS_FULL          <= FULL;
    end 



/*-----------------------------------------------------------------------------------
--  THE FOLLOWING CODE CREATES THE OCCUPANCY SIGNAL FOR CONFIGURABLE THRESHOLDS    --
--  Please refer to Xilinx Application Note 131 for an explanation of this logic.  --
-----------------------------------------------------------------------------------*/



// purpose: Reclock write pointer (Gray Code) onto FIFO_CLK.  
// type   : sequential
    always @(posedge FIFO_CLK)
    begin
      if(RX_FIFO_SRESET == 1'b1)
        HOST_WR_ADDRGRAY <= 0;
      else
        HOST_WR_ADDRGRAY <= WR_TRUEGRAY;
    end 



// purpose: Convert FIFO_CLK write pointer from Gray Code to Binary for 512 word FIFO.
// type   : combinatorial

    // Use the code below when Verilog 2001 generate statements are supported....
    /*    
    generate
      if(FIFO_SIZE == 512)
      begin
        assign HOST_WR_ADDR[8] = HOST_WR_ADDRGRAY[8];
        assign HOST_WR_ADDR[7] = HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7];
        assign HOST_WR_ADDR[6] = HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ HOST_WR_ADDRGRAY[6];
        assign HOST_WR_ADDR[5] = HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ HOST_WR_ADDRGRAY[6] ^
                           HOST_WR_ADDRGRAY[5];
        assign HOST_WR_ADDR[4] = HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ HOST_WR_ADDRGRAY[6] ^
                           HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4];
        assign HOST_WR_ADDR[3] = HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ HOST_WR_ADDRGRAY[6] ^
                           HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4] ^ HOST_WR_ADDRGRAY[3];
        assign HOST_WR_ADDR[2] = HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ HOST_WR_ADDRGRAY[6] ^
                           HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4] ^ HOST_WR_ADDRGRAY[3] ^
                           HOST_WR_ADDRGRAY[2];
        assign HOST_WR_ADDR[1] = HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ HOST_WR_ADDRGRAY[6] ^
                           HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4] ^ HOST_WR_ADDRGRAY[3] ^
                           HOST_WR_ADDRGRAY[2] ^ HOST_WR_ADDRGRAY[1];
        assign HOST_WR_ADDR[0] = HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ HOST_WR_ADDRGRAY[6] ^
                           HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4] ^ HOST_WR_ADDRGRAY[3] ^
                           HOST_WR_ADDRGRAY[2] ^ HOST_WR_ADDRGRAY[1] ^ HOST_WR_ADDRGRAY[0];
   	  end
   	  else if(FIFO_SIZE == 1024)
   	  begin
        assign HOST_WR_ADDR[9] = HOST_WR_ADDRGRAY[9];
        assign HOST_WR_ADDR[8] = HOST_WR_ADDRGRAY[9] ^ HOST_WR_ADDRGRAY[8];
        assign HOST_WR_ADDR[7] = HOST_WR_ADDRGRAY[9] ^ HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7];
        assign HOST_WR_ADDR[6] = HOST_WR_ADDRGRAY[9] ^ HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ 
                           HOST_WR_ADDRGRAY[6];
        assign HOST_WR_ADDR[5] = HOST_WR_ADDRGRAY[9] ^ HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ 
                           HOST_WR_ADDRGRAY[6] ^ HOST_WR_ADDRGRAY[5];
        assign HOST_WR_ADDR[4] = HOST_WR_ADDRGRAY[9] ^ HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ 
                           HOST_WR_ADDRGRAY[6] ^ HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4];
        assign HOST_WR_ADDR[3] = HOST_WR_ADDRGRAY[9] ^ HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ 
                           HOST_WR_ADDRGRAY[6] ^ HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4] ^ 
                           HOST_WR_ADDRGRAY[3];
        assign HOST_WR_ADDR[2] = HOST_WR_ADDRGRAY[9] ^ HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ 
                           HOST_WR_ADDRGRAY[6] ^ HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4] ^ 
                           HOST_WR_ADDRGRAY[3] ^ HOST_WR_ADDRGRAY[2];
        assign HOST_WR_ADDR[1] = HOST_WR_ADDRGRAY[9] ^ HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ 
                           HOST_WR_ADDRGRAY[6] ^ HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4] ^ 
                           HOST_WR_ADDRGRAY[3] ^ HOST_WR_ADDRGRAY[2] ^ HOST_WR_ADDRGRAY[1];
        assign HOST_WR_ADDR[0] = HOST_WR_ADDRGRAY[9] ^ HOST_WR_ADDRGRAY[8] ^ HOST_WR_ADDRGRAY[7] ^ 
                           HOST_WR_ADDRGRAY[6] ^ HOST_WR_ADDRGRAY[5] ^ HOST_WR_ADDRGRAY[4] ^ 
                           HOST_WR_ADDRGRAY[3] ^ HOST_WR_ADDRGRAY[2] ^ HOST_WR_ADDRGRAY[1] ^ 
                           HOST_WR_ADDRGRAY[0];