generic_transmit_fifo.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

    RAMB16_S1_S1 RAM_SIZE613
               (.DIA(WR_DATA[3:3]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[3:3])
                );

    RAMB16_S1_S1 RAM_SIZE614
               (.DIA(WR_DATA[4:4]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[4:4])
                );

    RAMB16_S1_S1 RAM_SIZE615
               (.DIA(WR_DATA[5:5]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[5:5])
                );

    RAMB16_S1_S1 RAM_SIZE616
               (.DIA(WR_DATA[6:6]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[6:6])
                );

    RAMB16_S1_S1 RAM_SIZE617
               (.DIA(WR_DATA[7:7]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[7:7])
                );

    RAMB16_S1_S1 RAM_SIZE618
               (.DIA(WR_DATA[8:8]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[8:8])
                );

    RAMB16_S1_S1 RAM_SIZE619
               (.DIA(WR_DATA[9:9]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[9:9])
                );

    RAMB16_S1_S1 RAM_SIZE6110
               (.DIA(WR_DATA[10:10]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[10:10])
                );

    RAMB16_S1_S1 RAM_SIZE6111
               (.DIA(WR_DATA[11:11]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[11:11])
                );

    RAMB16_S1_S1 RAM_SIZE6112
               (.DIA(WR_DATA[12:12]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[12:12])
                );

    RAMB16_S1_S1 RAM_SIZE6113
               (.DIA(WR_DATA[13:13]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[13:13])
                );

    RAMB16_S1_S1 RAM_SIZE6114
               (.DIA(WR_DATA[14:14]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[14:14])
                );

    RAMB16_S1_S1 RAM_SIZE6115
               (.DIA(WR_DATA[15:15]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[15:15])
                );

    RAMB16_S1_S1 RAM_SIZE6116
               (.DIA(WR_DATA[16:16]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[16:16])
                );

    RAMB16_S1_S1 RAM_SIZE6117
               (.DIA(WR_DATA[17:17]),
                .DIB(DUMMY9),
                .ENA(PWR),
                .ENB(RD_EN),
                .WEA(WR_EN),
                .WEB(GND),
                .SSRA(GND),
                .SSRB(TX_SRESET),
                .CLKA(CLK),
                .CLKB(TX_CLK),
                .ADDRA(WR_POINTER_VECTOR),
                .ADDRB(RD_POINTER_VECTOR),
                .DOB(RD_DATA_INT[17:17])
                );
    */   
    // STATUS_EMPTY is registered to recognise a falling edge
    always @(posedge TX_CLK)
    begin
      if (TX_SRESET == 1'b1)
        STATUS_EMPTY_INT_TX_REG <= 1'b1;
      else
        STATUS_EMPTY_INT_TX_REG <= STATUS_EMPTY_INT_TX; 
    end 
    
    // This signal ensures that no bounce is caused by the status going empty/not empty/empty
    always @(NEARLY_EMPTY_TX or STATUS_EMPTY_INT_TX or STATUS_EMPTY_INT_TX_REG or RD_DATA_INT[16])
    begin
      if (NEARLY_EMPTY_TX == 1'b0)
        EMPTY_VALID_COMB <= 1'b1;
      else if (STATUS_EMPTY_INT_TX == 1'b0 && STATUS_EMPTY_INT_TX_REG == 1'b1 && RD_DATA_INT[16] == 1'b0) 
        EMPTY_VALID_COMB <= 1'b0;
      else
        EMPTY_VALID_COMB <= 1'b1;
    end 
    
    always @(posedge TX_CLK)
    begin
      if (TX_SRESET == 1'b1)
        EMPTY_VALID <= 1'b1;
      else
        EMPTY_VALID <= EMPTY_VALID_COMB;
    end 
    
    // UNDERRUN is registered to ensure that this signal is valid before affecting internal
	// and external signals
    always @(posedge TX_CLK)
    begin
      if (TX_SRESET == 1'b1)
        INT_UNDERRUN_REG <= 1'b0;
      else
        INT_UNDERRUN_REG <= INT_UNDERRUN;
    end 
    
    
    // register memory read to help with timing but only when enabled
	// this allows the data to be pre-read from the RAM and then only read to the output when enabled
    always @(posedge TX_CLK)
    begin
      if (TX_SRESET == 1'b1)
        RD_DATA <= 0;
      else if (OUT_ENABLE == 1'b1)
        RD_DATA <= RD_DATA_INT;
    end
    
    // Reclock NEARLY_EMPTY into TX_CLK domain
    always @(posedge TX_CLK)
    begin
      if (TX_SRESET == 1'b1)
        NEARLY_EMPTY_SIZE_TX <= 1'b1;
	  else
        NEARLY_EMPTY_SIZE_TX <= NEARLY_EMPTY_SIZE;
    end

    assign NEARLY_EMPTY_FRAME_TX = FRAME_COUNT_EMPTY;

    assign NEARLY_EMPTY_TX = NEARLY_EMPTY_SIZE_TX & NEARLY_EMPTY_FRAME_TX;
    
	// Reclock frame count /= zero into TX_FIFO_CLK domain
	// It's classed as not being empty when there is 3 or more in the frame count
    // or just 2 and not transmitting
	always @(FRAME_COUNT or FRAME_COUNT_ZERO or FRAME_TRANSMIT_REG)
	begin
	  if ((FRAME_COUNT[log2_FIFO_SIZE-2:2] == FRAME_COUNT_ZERO) &&
		 (FRAME_COUNT[1] == 1'b0 || (FRAME_COUNT[0] == 1'b0 && FRAME_TRANSMIT_REG == 1'b1)))
		FRAME_COUNT_EMPTY_COMB <= 1'b1;
	  else
		FRAME_COUNT_EMPTY_COMB <= 1'b0;
	end

	always @(posedge TX_CLK)
	begin
	  if (TX_SRESET == 1'b1)
		FRAME_COUNT_EMPTY <= 1'b1;
	  else
		FRAME_COUNT_EMPTY <= FRAME_COUNT_EMPTY_COMB;
	end 

    // UP/DOWN counter to count how many frames are stored in FIFO
	// The frame count increases by two for every complete frame written -
	// once when the first word of a new frame is written and
	// once when the codeword is written.
	// Similarly the frame count reduces by two for every complete frame read -
	// once when the first word of a new frame is read and
	// once when the codeword is read.
	always @(FRAME_WRITE or FRAME_WRITE_REG or CODE_WRITE or CODE_WRITE_REG or FRAME_WRITE_ADD or FRAME_READ or FRAME_COUNT_ZERO or FRAME_COUNT)
    begin
	  if (((FRAME_WRITE == 1'b1 && FRAME_WRITE_REG == 1'b0) ||
					(CODE_WRITE == 1'b1 && CODE_WRITE_REG == 1'b0) ||
					FRAME_WRITE_ADD == 1'b1) && FRAME_READ == 1'b0)
	    FRAME_COUNT_COMB <= FRAME_COUNT + {FRAME_COUNT_ZERO, 2'b01};
	  else if (FRAME_READ == 1'b1 && ~((FRAME_WRITE == 1'b1 && FRAME_WRITE_REG == 1'b0) ||
					(CODE_WRITE == 1'b1 && CODE_WRITE_REG == 1'b0) ||
					FRAME_WRITE_ADD == 1'b1))
		FRAME_COUNT_COMB <= FRAME_COUNT - {FRAME_COUNT_ZERO, 2'b01};
	  else 
	    FRAME_COUNT_COMB <= FRAME_COUNT;
	end 

    always @(posedge TX_CLK)
    begin
      if (TX_SRESET == 1'b1)
		FRAME_COUNT <= 0;