generic_transmit_fifo.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

///////////////////////////////////////////////////////////////////////////////
//
//      Project:  1 Gig Ethernet MAC FIFO Reference Design
//      Version:  2.0
//      File   :  generic_transmit_fifo.v
//
//      Company:  Xilinx
// Contributors:  Xilinx Inc.
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// Generic 1 Gig MAC Transmit Interface
// Author: Xilinx Inc.
//
// Description: This module provides a generic interface between the host and
//              the transmit part of the 1Gig MAC.  The host interface consists
//              of a 16-bit data bus, a 2-bit lane_valid signal and appropriate
//              write and clock signals.  The MAC interface provides the 
//              specified protocol interface for the 1Gig-MAC.  Status signals, 
//              including FULL, NEARLY_FULL, NEARLY_EMPTY and EMPTY are 
//              provided.  Status signals UNDERRUN and OVERLOAD are provided to 
//              indicate to the host if the FIFO ran out of data when 
//              transmitting to the MAC (underrun) or if the host tried to 
//              write to the FIFO when it was full (overload).
//              Automatic protection of the FIFO is provided to ensure that old
//              data cannot be overwritten before it is read.
//
///////////////////////////////////////////////////////////////////////////////
// Interface Description: The data input to the FIFO (DATA) is a 16-bit wide 
//                        signal, consisting of 2 bytes.  Each byte is 
//                        validated by the LANE_VALID input where each bit of 
//                        LANE_VALID indicates if the appropriate byte of DATA 
//                        is valid (1) or invalid (0).  Therefore a 1 on 
//                        LANE_VALID(0) would indicate that DATA(7 downto 0) 
//                        was valid data. 
//                        To perform a write operation into the FIFO, the 
//                        appropriate data must be available on the DATA input
//                        with the corresponding LANE_VALID set, while the 
//                        WR_ENABLE input is held high through a rising edge of 
//	                  a CLK pulse.  If the write is going to be successful, 
//                        the ACK output will be high in the same clock cycle.
//                        However, if the write is not possible (perhaps the
//                        FIFO is full) then the ERR output will be high in
//                        the same clock cycle.  The outputs ACK and ERR are
//                        complimentary. STATUS_FULL indicates when high that
//                        there is no more space in the FIFO - any attempts to 
//	                  write data will be disallowed and an ERR returned.                      
//                        STATUS_EMPTY indicates when high that there is no data
//                        in the FIFO.  If this condition occurrs while
//                        transmitting a frame to the MAC, this will cause an
//                        error, and the FIFO will inform the MAC to corrupt
//                        that frame.
//                        STATUS_UNDERRUN indicates when high that the above
//                        error has occurred.  It is reset when a codeword is
//                        written into the FIFO. STATUS_OVERLOAD indicates when
//                        high that there has been an attempt to write to the
//                        FIFO when it was full.  It is reset when a codeword 
//                        is written into the FIFO.
//                        STATUS_NEARLY_FULL indicates when high that there is
//                        more words of data in the FIFO than the amount
//                        indicated by the NEARLY_FULL_THRESH signal.  This
//                        signal comes from the configuration block and can 
//	                  therefore be independently configured to the required
//	                  value.
//                        STATUS_NEARLY_EMPTY indicates when high that there is
//                        the same amount or less words of data in the FIFO
//                        than the amount indicated by the NEARLY_EMPTY_THRESH
//                        signal.  This signal comes from the configuration 
//                        block and can therefore be independently configured
//                        to the required value.
//                        The signals to and from the MAC provide the necessary
//                        interface for the transmit side of the MAC.
//
///////////////////////////////////////////////////////////////////////////////
// Operation: Data can be written into the FIFO at any speed between 10 MHz and
//            150 MHz in 16-bit words.  It is not necessary to write complete
//            frames all at once. However, at the end of each frame a codeword
//            must be written.  This codeword is  recognised because 
//            LANE_VALID(0) = 0 which is usually an illegal condition, as most 
//            words will have all of LANE_VALID = 1 and only the final word of
//            the frame may  possibly not have all data in the data word being
//            used.  If it is required to scrap  the frame that has just been 
//            written into the FIFO, then DATA(15) should be set high when this 
//            control word is written.  If the FIFO fills up in the middle of a 
//            frame, so that any further writes are met with ERR going high,
//            there will still be  one word left free to write a codeword if 
//            required.
//            The FIFO will only start transmitting a frame to the MAC once
//            the amount of data stored in the FIFO is more than the amount
//            of words indicated by the NEARLY_EMPTY_THRESH signal.  This
//            condition is also indicated by STATUS_NEARLY_EMPTY going low.  
//            The FIFO will then transmit the frame to the MAC as indicated by
//            the  MAC protocol.  If the FIFO runs out of data before it has
//            completed transmitting the frame, the MAC will be told to scrap
//            that frame and STATUS_UNDERRUN will be set high.  If the frame
//            completes successfully, another frame will not be sent until 
//            there are more words in the FIFO than the NEARLY_EMPTY_THRESH
//            signal as before.  The data in the FIFO needs to be split into
//            two words before sending to the MAC, as the MAC accepts 8-bit 
//            data rather than 16-bit words.
//
///////////////////////////////////////////////////////////////////////////////
// Design: The FIFO is implemented in block ram to utilise the features of
//         Virtex2.  The full and empty conditions are calculated by first
//         converting the write and read pointers into gray code and then 
//         comparing them.  This ensures that the comparison will only be one 
//         position out.  The full and empty flags then work in a pessimistic
//         way, so that if the FIFO is one away from full then the flag will
//         go up if there is an attempt to make a write.  However, during this
//         time, there may have been a read, but this will not be determined 
//         until the next clock.  A similar situation exists for the empty flag.
//         This results in the flags going high when it may not be necessary,
//         or staying high longer than they should, but it does ensure that the 
//         FIFO never writes over any data.
//
///////////////////////////////////////////////////////////////////////////////
// Generics: The FIFO size can be chosen by passing in an integer generic: 
//           FIFO_SIZE.  The choices for the different sizes are: 512, 1024,
//           2048, 4096, 8192 or 16384 words, all 16-bit wide.
//
///////////////////////////////////////////////////////////////////////////////


`timescale 1 ps / 1 ps	

module GENERIC_TRANSMIT_FIFO
  (//------------------------------------------------------------
   // Host interface --
   //------------------------------------------------------------
   CLK,
   TX_SRESET,
   TX_FIFO_SRESET,
   LANE_VALID,
   DATA,
   WR_ENABLE,
   ACK,
   ERR,
   STATUS_FULL,
   STATUS_NEARLY_FULL,
   STATUS_NEARLY_EMPTY,
   STATUS_EMPTY,
   STATUS_UNDERRUN,
   STATUS_OVERLOAD,      
   //-------------------------------------------------------------
   // Internal Interface --
   //-------------------------------------------------------------
   NEARLY_EMPTY_THRESH,
   NEARLY_FULL_THRESH,
   //-------------------------------------------------------------
   // MAC Transmit Interface --
   //-------------------------------------------------------------
   TX_CLK,
   TX_ACK,
   TX_DATA_VALID,
   TX_DATA,
   TX_UNDERRUN_OUT);
   
   // CHANGES REQUIRED
   parameter FIFO_SIZE = 1024;   // The size of the FIFO can be 512, 1024, 2048, 4096, 8192 or 16384 words long
   // Other params used only internally...
   parameter log2_FIFO_SIZE = (FIFO_SIZE == 512 ? 9 : 
                                 (FIFO_SIZE == 1024 ? 10 :
                                     (FIFO_SIZE == 2048 ? 11 :
                                       (FIFO_SIZE == 4096 ? 12 :
                                         (FIFO_SIZE == 8192 ? 13 : 14)))));

   //------------------------------------------------------------
   // Host interface --
   //------------------------------------------------------------
      
   input CLK;                   // Bus clock
   input TX_SRESET;             // Synchronous reset - TX_CLK
   input TX_FIFO_SRESET;        // Synchronous reset - TX_FIFO_CLK
   input [1:0] LANE_VALID;      // Indication of what bytes are valid in DATA
   input [15:0] DATA;           // Data to be written from bus
   input WR_ENABLE;             // Write the contents of DATA into FIFO
   output ACK;                  // Acknowledge to bus that data was written
   output ERR;                  // Acknowledge to bus that dat could not be written
   output STATUS_FULL;          // Status indicator that FIFO is full
   output STATUS_NEARLY_FULL;   // Status indicator that FIFO is almost full
   output STATUS_NEARLY_EMPTY;  // Status indicator that FIFO is almost empty
   output STATUS_EMPTY;         // Status indicator that FIFO is empty
   output STATUS_UNDERRUN;      // Status indicator that FIFO has underrun
   output STATUS_OVERLOAD;      // Status indicator that FIFO has overloaded
         
   //-------------------------------------------------------------
   // Internal Interface --
   //-------------------------------------------------------------
   
   input [log2_FIFO_SIZE-1:0] NEARLY_EMPTY_THRESH;  // Configurable threshold for the NEARLY_EMPTY flag
   input [log2_FIFO_SIZE-1:0] NEARLY_FULL_THRESH;   // Configurable threshold for the NEARLY_FULL flag
   
   //-------------------------------------------------------------
   // MAC Transmit Interface --
   //-------------------------------------------------------------
   
   input TX_CLK;            // MAC Transmit clock
   input TX_ACK;            // MAC Transmit acknowledge
   output TX_DATA_VALID;    // Indication of what bytes are valid in TX_DATA
   output [7:0] TX_DATA;    // Data to be written to MAC
   output TX_UNDERRUN_OUT;  // Force MAC to scrap current frame

   parameter COUNT_WIDTH = log2_FIFO_SIZE;   // Determine the binary width of the FIFO_SIZE selected
   
   wire TX_DATA_VALID;    // Indication of what bytes are valid in TX_DATA
   reg [7:0] TX_DATA;    // Data to be written to MAC
   reg TX_UNDERRUN_OUT;  // Force MAC to scrap current frame

   reg [COUNT_WIDTH-1:0] WR_POINTER;         // Write pointer
   reg [COUNT_WIDTH-1:0] WR_POINTER_COMB;   // Write pointer
   reg [COUNT_WIDTH-1:0] RD_POINTER;         // Read pointer
   wire [COUNT_WIDTH-1:0] WR_POINTER_VECTOR;  // std_logic_vector versions
   wire [COUNT_WIDTH-1:0] RD_POINTER_VECTOR;
   wire [17:0] WR_DATA;                      // Write data to FIFO including data and lane
   reg [17:0] RD_DATA;                       // Enabled, Registered version of Read data from FIFO including data and lane
   wire VALID_EN;                             // Enable signal for TX_DATA_VALID to bring this signal low during codewords
   reg DATA_VALID;                          // Multiplexed LANE_VALID read
   wire INT_NEARLY_FULL;                      // Combined NEARLY_FULL and FULL signal
   wire RD_EN;                                // Read enable signal for FIFO
   wire WR_EN;                                // Write enable signal for FIFO
   reg UNDERRUN_PULSE;                       // Forced underrun pulse from codeword
   reg INT_UNDERRUN;                         // Internal UNDERRUN
   reg INT_UNDERRUN_COMB;                   // Internal UNDERRUN
   reg HALF_BIT;                             // selection bit to determine which half of the data word is transmitted
   reg HALF_BIT_COMB;                       // selection bit to determine which half of the data word is transmitted
   reg FULL;                                 // CLK synchronous FULL signal
   wire REALLY_EMPTY;                         // TX_CLK synchronous EMPTY signal
   reg NEARLY_FULL;                          // CLK synchronous NEARLY_FULL signal
   reg NEARLY_EMPTY;                         // TX_CLK synchronous NEARLY_EMPTY signal
   wire RD_INC;                               // Read pointer increment
   wire WR_INC;                               // Write pointer increment
   wire WRITE_ENABLE;                         // WR_INC before being validated by not FULL
   wire READ_ENABLE;                          // RD_INC before being validated by not REALLY_EMPTY
   wire [31:0] DUMMY1;         // Dummy signals for unused inputs
   wire [3:0] DUMMY2;
   wire [15:0] DUMMY3;
   wire [1:0] DUMMY4;
   wire [7:0] DUMMY5;
   wire [0:0] DUMMY6;
   wire [3:0] DUMMY7;
   wire [1:0] DUMMY8;
   wire [0:0] DUMMY9;
   reg UNDERRUN_SEL;                         // Selection signal for the UNDERRUN pulse generation multiplexer
   reg UNDERRUN_SEL_COMB;                   // Selection signal for the UNDERRUN pulse generation multiplexer
   wire FULL_ALLOW;                           // Internal signal to indicate update for FULL signal
   wire EMPTY_ALLOW;                          // Internal signal to indicate update for REALLY_EMPTY signal
   wire FULLG;                                // Combinatorial version of FULL
   wire EMPTYG;                               // Combinatorial version of REALLY_EMPTY
   reg [COUNT_WIDTH-1:0] READ_NEXTGRAY;      // Combinatorial version of READ_ADDRGRAY
   reg [COUNT_WIDTH-1:0] READ_ADDRGRAY;      // Gray code version of RD_POINTER
   reg [COUNT_WIDTH-1:0] READ_LASTGRAY;      // Old gray code version of RD_POINTER
   reg [COUNT_WIDTH-1:0] WRITE_NEXTGRAY;     // Combinatorial version of WRITE_ADDRGRAY
   reg [COUNT_WIDTH-1:0] WRITE_ADDRGRAY;     // Gray code version of WR_POINTER
   wire [COUNT_WIDTH-1:0] ECOMP;             // Compare signal for REALLY_EMPTY
   wire [COUNT_WIDTH-1:0] FCOMP;             // Compare signal for FULL
   wire [COUNT_WIDTH-1:0] EMUXCYO;           // Compare signal for REALLY_EMPTY
   wire [COUNT_WIDTH-1:0] FMUXCYO;           // Compare signal for FULL
   wire GND;
   assign GND = 1'b0;
   wire PWR;
   assign PWR = 1'b1;
   wire NEARLY_FULL_ALLOW;                    // Internal signal to indicate update for NEARLY_FULL signal
   wire NEARLY_FULLG;                         // Combinatorial version of NEARLY_FULL
   reg [COUNT_WIDTH-1:0] READ_PREVLASTGRAY;  // Old gray code version of READ_LASTGRAY
   wire [COUNT_WIDTH-1:0] NFCOMP;            // Compare signal for NEARLY_FULL
   wire [COUNT_WIDTH-1:0] NFMUXCYO;          // Compare signal for NEARLY_FULL
   reg [COUNT_WIDTH-1:0] READ_TRUEGRAY;      // Current gray code version of RD_POINTER
   reg [COUNT_WIDTH-1:0] RAG_WRITESYNC;      // read_truegray synchronised with CLK
   wire [COUNT_WIDTH-1:0] RA_WRITESYNC;       // Binary converted rag_writesync
   reg [COUNT_WIDTH-1:0] WRITE_ADDRR;        // Pipelined version of WR_POINTER
   reg [COUNT_WIDTH-1:0] FIFOSTATUS;         // WR-RD to allow check for NEARLY_EMPTY
   wire [2:0] XOROUT;                        // Internal signal to reduce xor statement
   reg START;                                // Internal TX_START
   reg STREAM;                               // Set to high after reception of ACK from transmitter to indicate stream mode
   reg STREAM_COMB;                         // Set to high after reception of ACK from transmitter to indicate stream mode
   wire CONTROL;                              // Indication that FIFO word is data (1'b1) or control word (1'b0)
   wire NEARLY_EMPTY_TX;                      // TX_CLK version of NEARLY_EMPTY
   wire [17:0] RD_DATA_INT;                   // Read data from FIFO including data and lane
   reg [7:0] TX_DATA_INT;                    // Internal TX_DATA
   reg DATA_VALID_INT;                       // Internal DATA_VALID
   reg START_REG;                            // START held until STREAM goes high 
   reg START_REG_COMB;                      // START held until STREAM goes high 
   wire MULT_SEL;                             // Selection for the READ_DATA multiplexer
   wire OUT_ENABLE;                           // Enables the registering of RD_DATA_INT
   reg INT_UNDERRUN_REG;                     // Registered version of INT_UNDERRUN
   wire TX_UNDERRUN;                          // Internal version of TX_UNDERRUN_OUT
   reg PRE_READ_ENABLE;                      // Front load some of the signals required to create READ_ENABLE to help with timing
   reg PRE_FULL;                             // full-1
   reg EMPTY_VALID;                          // Signal to indicate state of REALLY_EMPTY and NEARLY_EMPTY signals to determine which direction the FIFO is filling or unfilling
   reg STATUS_OVERLOAD_COMB;                // Internal version of STATUS_EMPTY
   reg STATUS_OVERLOAD_INT;                  // Internal version of STATUS_EMPTY
   reg STATUS_EMPTY_INT;                     // Internal version of STATUS_EMPTY
   reg STATUS_EMPTY_INT_TX;                  // TX_CLK version of STATUS_EMPTY_INT
   reg STATUS_EMPTY_INT_TX_REG;              // Registered version of STATUS_EMPTY_INT_TX
   wire [COUNT_WIDTH-1:0] RA_WRITESYNC_UNSIGNED;   // RA_WRITESYNC converted to unsigned
   wire [COUNT_WIDTH-1:0] FIFOSTATUS_EARLY;   // Unsigned, combinatorial version of FIFOSTATUS
   wire RD_EN_TEMP;
   reg [COUNT_WIDTH-2:0] FRAME_COUNT;        // Count how many frames in FIFO (max of 5 times smaller than FIFO)
   wire [COUNT_WIDTH-4:0] FRAME_COUNT_ZERO;
   wire FRAME_READ;	                         // Indicates when a frame is starting to be read
   reg FRAME_WRITE_FIFO;                     // Indicates when a frame has been written in clk domain
   reg FRAME_WRITE_FIFO_COMB;               // Indicates when a frame has been written in clk domain
   reg FRAME_WRITE_FIFO_HOLD;                // Indicates when a frame has been written in clk domain
   reg FRAME_WRITE_FIFO_HOLD_COMB;          // Indicates when a frame has been written in clk domain
   reg FRAME_WRITE;                          // Indicate when a frame has been written in tx_clk domain
   reg FRAME_WRITE_REG;
   reg FRAME_COUNT_EMPTY;                    // Indicate when FRAME_COUNT is zero
   reg FRAME_COUNT_EMPTY_COMB;              // Indicate when FRAME_COUNT is zero
   reg FRAME_WRITE_ADD;
   reg FRAME_WRITE_ADD_COMB;
   reg CODE_WRITE;                           // Indicate when a code has been written in tx_clk domain
   reg CODE_WRITE_REG;
   reg CODE_WRITE_FIFO;
   reg CODE_WRITE_FIFO_COMB;
   
   reg PRE_READ_ENABLE_COMB;
   reg EMPTY_VALID_COMB;
   reg [COUNT_WIDTH-2:0] FRAME_COUNT_COMB;   
   reg START_COMB;

   wire [31:0] RD_TEMP1;
   wire [3:0] RD_TEMP2;
   wire [3:0] RD_TEMP3;
   
   wire [31:0] WR_DATA_PADDED;
   wire [3:0] WR_VLD_PADDED;
   wire [3:0] WR_DATA_PAD2;