gmac_fifo.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

   output PAUSE_REQ;            // Causes MAC Flow Control to send Pause Frame.
   output [15:0] PAUSE_VAL;     // Pause Quanta Period of requested pause. 

      //--------------------------------------------------------------
      // Client interface                                           --
      //--------------------------------------------------------------

   input WrClk;                 // The Transmit Client Clock.                               
   input RdClk;                 // The Receive Client Clock.

   input RdEn;                  // Read the contents of RX_FIFO.
   output RdAck;                // Data was successfully read from RX_FIFO.        
   output Underflow;            // Data was not successfully read from RX_FIFO.        
   output [23:0] RdData;        // Data to be read by Client Bus.                                    
//      RX_FIFO_DATA_VALID     = RdData(17..16)               // Indicates valid bytes of RD_FIFO_DATA.                             
//      RX_STATUS_FULL         = RdData(18)                   // Status indicator that RX_FIFO is full. 
//      RX_STATUS_NEARLY_FULL  = RdData(19)                   // Status indicator that RX_FIFO is almost full.        
//      TX_STATUS_EMPTY        = RdData(20)                   // Status indicator that TX_FIFO is empty.
//      TX_STATUS_NEARLY_EMPTY = RdData(21)                   // Status indicator that TX_FIFO is almost empty.
//      TX_STATUS_UNDERRUN     = RdData(22)                   // Status indicator that TX_FIFO has underrun.
//      TX_STATUS_OVERLOAD     = RdData(23)                   // Status indicator that TX_FIFO has overloaded.
   output Empty;                // Status indicator that RX_FIFO is empty.        
   output AlmostEmpty;          // Status indicator that RX_FIFO is almost empty.         
   input [17:0] WrData;         // Data to be written from Client Bus.
//      TX_FIFO_DATA_VALID = WrData(17..16)   // Indicates valid bytes of WR_DATA.
   input WrEn;                  // Write the contents of WR_FIFO_DATA into TX_FIFO.
   output WrAck;                // Data was successfully written to TX_FIFO.
   output Overflow;             // Data was not successfully written to TX_FIFO.
   output Full;                 // Status indicator that TX_FIFO is full.
   output AlmostFull;           // Status indicator that TX_FIFO is almost full.

      //--------------------------------------------------------------
      // Management Interface                                       --
      //--------------------------------------------------------------

   input HOST_CLK;              // The Host Clock.                               
   input [9:0] HOST_ADDR;       // Host Address bus.   
   output [31:0] HOST_RD_DATA;  // Host output (read) data bus.  
   input [31:0] HOST_WR_DATA;   // Host input (write) data bus.  
   input HOST_RNW;              // Host Read/Write Strobe, 0 = write, 1 = read.                     

   parameter C_TX_FIFO_DEPTH = 1024;
   parameter C_RX_FIFO_DEPTH = 1024;   // Valid FIFO sizes: 512, 1024, 2048, 4096, 8192, 16384 words.

   parameter log2_RX_FIFO_SIZE = (C_RX_FIFO_DEPTH == 512 ? 9 : 
                                   (C_RX_FIFO_DEPTH == 1024 ? 10 :
                                     (C_RX_FIFO_DEPTH == 2048 ? 11 :
                                       (C_RX_FIFO_DEPTH == 4096 ? 12 :
                                         (C_RX_FIFO_DEPTH == 8192 ? 13 : 14)))));

   parameter log2_TX_FIFO_SIZE = (C_TX_FIFO_DEPTH == 512 ? 9 : 
                                   (C_TX_FIFO_DEPTH == 1024 ? 10 :
                                     (C_TX_FIFO_DEPTH == 2048 ? 11 :
                                       (C_TX_FIFO_DEPTH == 4096 ? 12 :
                                         (C_TX_FIFO_DEPTH == 8192 ? 13 : 14)))));

   wire [log2_TX_FIFO_SIZE-1:0] TX_NEARLY_EMPTY_THRESH; // Used to produce TX_STATUS_NEARLY_EMPTY.
   wire [log2_TX_FIFO_SIZE-1:0] TX_NEARLY_FULL_THRESH;  // Used to produce TX_STATUS_NEARLY_FULL.
   wire [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_EMPTY_THRESH;
   wire [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_FULL_HIGH_THRESH;
   wire [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_FULL_LOW_THRESH;
   wire [15:0] PAUSE_TIME;                              // Number of Pause Quanta.
   wire STATUS_NEARLY_FULL_HIGH;                        // Rx FIFO is Nearly Full.
   wire STATUS_NEARLY_FULL_LOW;                         // Rx FIFO is Nearly Full.                              
   wire FLOW_CTRL_EN;                                   // Enable flow control
   wire PAUSE_REQ_MAN;                                  // Manual pause req
   wire RX_SRESET;							 	        // Synchronous reset
   wire TX_SRESET;
   wire RX_FIFO_SRESET;
   wire TX_FIFO_SRESET;


// purpose: Assign outputs to internal signals
// type   : routing
   assign RdData[19] = STATUS_NEARLY_FULL_HIGH;

// purpose: FIFO Interface to MAC Transmitter Logic
// type   : component
   GENERIC_TRANSMIT_FIFO #(C_TX_FIFO_DEPTH) TX_FIFO
     (
      .CLK(WrClk),  
      .TX_SRESET(TX_SRESET),
      .TX_FIFO_SRESET(TX_FIFO_SRESET),  
      .LANE_VALID(WrData[17:16]),           
      .DATA(WrData[15:0]),                
      .WR_ENABLE(WrEn),               
      .ACK(WrAck),                  
      .ERR(Overflow),                  
      .STATUS_FULL(Full),          
      .STATUS_NEARLY_FULL(AlmostFull),         
      .STATUS_NEARLY_EMPTY(RdData[21]),   
      .STATUS_EMPTY(RdData[20]),  
      .STATUS_UNDERRUN(RdData[22]),      
      .STATUS_OVERLOAD(RdData[23]),      
      .NEARLY_EMPTY_THRESH(TX_NEARLY_EMPTY_THRESH),   
      .NEARLY_FULL_THRESH(TX_NEARLY_FULL_THRESH),
      .TX_CLK(TX_CLK),         
      .TX_ACK(TX_ACK),         
      .TX_DATA_VALID(TX_DATA_VALID),  
      .TX_DATA(TX_DATA),        
      .TX_UNDERRUN_OUT(TX_UNDERRUN)
     );



// purpose: FIFO Interface to MAC Receiver Logic
// type   : component
   GENERIC_RECEIVE_FIFO #(C_RX_FIFO_DEPTH) RX_FIFO
     (
      .RX_CLK(RX_CLK),             
      .RX_SRESET(RX_SRESET),
      .RX_FIFO_SRESET(RX_FIFO_SRESET),              
      .RX_DATA(RX_DATA),            
      .RX_DATA_VALID(RX_DATA_VALID),      
      .GOOD_FRAME(RX_GOOD_FRAME),         
      .BAD_FRAME(RX_BAD_FRAME),          
      .FIFO_CLK(RdClk),           
      .RD_ENABLE(RdEn),
      .NEARLY_EMPTY_THRESH(RX_NEARLY_EMPTY_THRESH),
      .NEARLY_FULL_HIGH_THRESH(RX_NEARLY_FULL_HIGH_THRESH),         
      .NEARLY_FULL_LOW_THRESH(RX_NEARLY_FULL_LOW_THRESH),                    
      .RD_ACK(RdAck),             
      .RD_ERR(Underflow),             
      .DATA_OUT(RdData[15:0]),           
      .DATA_VALID_OUT(RdData[17:16]),     
      .STATUS_FULL(RdData[18]),        
      .STATUS_EMPTY(Empty),       
      .STATUS_NEARLY_FULL_HIGH(STATUS_NEARLY_FULL_HIGH), 
      .STATUS_NEARLY_FULL_LOW(STATUS_NEARLY_FULL_LOW), 
      .STATUS_NEARLY_EMPTY(AlmostEmpty)
      );



// purpose: Pause Control of Client Interface
// type   : component
   FIFO_PAUSE_CONTROL PAUSE_LOGIC
     (
      .TX_CLK(TX_CLK),    
      .TX_SRESET(TX_SRESET),     
      .PAUSE_AUTO_ENABLE(FLOW_CTRL_EN),
      .PAUSE_REQ_MAN(PAUSE_REQ_MAN),
      .STATUS_NEARLY_FULL_HIGH(STATUS_NEARLY_FULL_HIGH),
      .STATUS_NEARLY_FULL_LOW(STATUS_NEARLY_FULL_LOW),              
      .PAUSE_VALUE_IN(PAUSE_TIME),      
      .PAUSE_VALUE_OUT(PAUSE_VAL),      
      .PAUSE_REQ_OUT(PAUSE_REQ)   
     );

      
      
// purpose:  Configuration Block for 10 Gig Ethernet MAC FIFO Reference Design
// type   : component
   CONFIGURE #(C_TX_FIFO_DEPTH, C_RX_FIFO_DEPTH) BACKEND_CONFIG
     (
      .HOST_CLK(HOST_CLK),
      .TX_FIFO_CLK(WrClk),
      .RX_FIFO_CLK(RdClk),
      .TX_CLK(TX_CLK),    
      .RX_CLK(RX_CLK),    
      .RESET(RESET),
      .ADDR(HOST_ADDR),   
      .RD_DATA(HOST_RD_DATA),
      .WR_DATA(HOST_WR_DATA),
      .W_R(HOST_RNW),    
      .TX_NEARLY_EMPTY_THRESH(TX_NEARLY_EMPTY_THRESH),  
      .TX_NEARLY_FULL_THRESH(TX_NEARLY_FULL_THRESH),
      .TX_SRESET_OUT(TX_SRESET),
      .RX_NEARLY_EMPTY_THRESH(RX_NEARLY_EMPTY_THRESH),
      .RX_NEARLY_FULL_HIGH_THRESH(RX_NEARLY_FULL_HIGH_THRESH),
      .RX_NEARLY_FULL_LOW_THRESH(RX_NEARLY_FULL_LOW_THRESH),
      .RX_SRESET_OUT(RX_SRESET),
      .PAUSE_VALUE(PAUSE_TIME),
      .PAUSE_REQ(PAUSE_REQ_MAN),
      .FLOW_CTRL_EN(FLOW_CTRL_EN),
      .TX_FIFO_SRESET_OUT(TX_FIFO_SRESET),
      .RX_FIFO_SRESET_OUT(RX_FIFO_SRESET)          
     ); 

			   
endmodule