configure.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

   begin
     if (HOST_SRESET == 1'b1)
     begin
       RD_DATA  <= 32'h00000000;
     end
     else
     begin
       case (ADDR[9:3])
         7'b1110000 : 
         begin
            RD_DATA[31:log2_TX_FIFO_SIZE+16] <= 0;
            RD_DATA[log2_TX_FIFO_SIZE+15:16] <= TX_NEARLY_FULL_THRESHOLD;
            RD_DATA[15:log2_TX_FIFO_SIZE]    <= 0;
            RD_DATA[log2_TX_FIFO_SIZE-1:0]   <= TX_NEARLY_EMPTY_THRESHOLD;
         end
         7'b1110001 : 
         begin
            RD_DATA[31:log2_RX_FIFO_SIZE+16] <= 0;
            RD_DATA[log2_RX_FIFO_SIZE+15:16] <= RX_NEARLY_FULL_LOW_THRESHOLD;
            RD_DATA[15:log2_RX_FIFO_SIZE]    <= 0;
            RD_DATA[log2_RX_FIFO_SIZE-1:0]   <= RX_NEARLY_FULL_HIGH_THRESHOLD;
         end
         7'b1110010 :
         begin
            RD_DATA[31:log2_RX_FIFO_SIZE]    <= 0;
            RD_DATA[log2_RX_FIFO_SIZE-1:0]   <= RX_NEARLY_EMPTY_THRESHOLD;
         end
         7'b1110011 :
         begin
            RD_DATA[31:17]                   <= 0;
            RD_DATA[16]                      <= FLOW_CTRL_ENABLE;
            RD_DATA[15:0]                    <= PAUSE_TIME;
         end
         default    : 
            RD_DATA                          <= 0;
       endcase
     end
   end 



// purpose: Reclock the Pause Value from HOST_CLK to TX_CLK 
// type   : sequential
   always @(posedge TX_CLK)
   begin
     if (TX_SRESET == 1'b1)
     begin
       PAUSE_VALUE  <= 16'h0000;
       PAUSE_REQ    <= 1'b0;
       FLOW_CTRL_EN <= 1'b1;
     end
     else
     begin
       PAUSE_VALUE  <= PAUSE_TIME;
       PAUSE_REQ    <= PAUSE_REQUEST;
       FLOW_CTRL_EN <= FLOW_CTRL_ENABLE;
	 end 
   end 



// purpose: Reclock the Receiver Thresholds from HOST_CLK to RX_FIFO_CLK 
// type   : sequential
   always @(posedge RX_FIFO_CLK)
   begin
     if (RX_FIFO_SRESET == 1'b1)
     begin
       RX_NEARLY_EMPTY_THRESH[log2_RX_FIFO_SIZE-1:4]     <= 0;
       RX_NEARLY_EMPTY_THRESH[3:0]                       <= 4'b1111;
       RX_NEARLY_FULL_HIGH_THRESH[log2_RX_FIFO_SIZE-1:8] <= 0;
       RX_NEARLY_FULL_HIGH_THRESH[7:0]                   <= 8'b11111111;
       RX_NEARLY_FULL_LOW_THRESH[log2_RX_FIFO_SIZE-1:6]  <= 0;
       RX_NEARLY_FULL_LOW_THRESH[5:0]                    <= 6'b111111;
     end
     else
     begin
       RX_NEARLY_EMPTY_THRESH     <= RX_NEARLY_EMPTY_THRESHOLD;
       RX_NEARLY_FULL_HIGH_THRESH <= RX_NEARLY_FULL_HIGH_THRESHOLD;
       RX_NEARLY_FULL_LOW_THRESH  <= RX_NEARLY_FULL_LOW_THRESHOLD;
	 end 
   end



// purpose: Reclock the Transmitter Thresholds from HOST_CLK to TX_FIFO_CLK 
// type   : sequential
   always @(posedge TX_FIFO_CLK)
   begin
     if (TX_FIFO_SRESET == 1'b1)
     begin
       TX_NEARLY_EMPTY_THRESH[log2_TX_FIFO_SIZE-1:4] <= 0;
       TX_NEARLY_EMPTY_THRESH[3:0]            <= 4'b1111;
       TX_NEARLY_FULL_THRESH[log2_TX_FIFO_SIZE-1:8]  <= 0;
       TX_NEARLY_FULL_THRESH[7:0]             <= 8'b11111111;
     end
     else
     begin
       TX_NEARLY_EMPTY_THRESH <= TX_NEARLY_EMPTY_THRESHOLD;
       TX_NEARLY_FULL_THRESH  <= TX_NEARLY_FULL_THRESHOLD;
     end
   end 

   always @(posedge HOST_CLK)
   begin
     if (HOST_SRESET == 1'b1)
     begin
       RX_RESET <= 1'b0;
       TX_RESET <= 1'b0;
     end
	 else if (W_R == 1'b0)
	 begin
       case (ADDR[9:3])
         7'b1110000 : 
         begin
           TX_RESET <= WR_DATA[31];
		   RX_RESET <= 1'b0;
         end
         7'b1110001 : 
         begin
           RX_RESET <= WR_DATA[31];
		   TX_RESET <= 1'b0;
         end
         default :     
         begin
           RX_RESET <= 1'b0;
		   TX_RESET <= 1'b0;
         end
       endcase
     end
     else
     begin
	   RX_RESET <= 1'b0;
	   TX_RESET <= 1'b0;
     end
   end 
   
   assign COMB_RESET_TX = RESET | TX_RESET;
   assign COMB_RESET_RX = RESET | RX_RESET;
   assign COMB_SRESET_TX = RESET | TX_SRESET;
   assign COMB_SRESET_RX = RESET | RX_SRESET;
   
   // Babysitting circuits to convert asynchronous reset into synchronous reset for each clock domain
   always @(posedge TX_CLK or posedge COMB_RESET_TX)
   begin
	 if (COMB_RESET_TX == 1'b1)
	 begin
	   TX_SRESET_PIPE <= 1'b1;
	   TX_SRESET      <= 1'b1;
     end
	 else 
	 begin
	   TX_SRESET_PIPE <= 1'b0;
	   TX_SRESET      <= TX_SRESET_PIPE;
	 end 
   end 

   always @(posedge RX_CLK or posedge COMB_RESET_RX)
   begin
	 if (COMB_RESET_RX == 1'b1)
	 begin
	   RX_SRESET_PIPE <= 1'b1;
	   RX_SRESET      <= 1'b1;
     end
	 else 
	 begin
	   RX_SRESET_PIPE <= 1'b0;
	   RX_SRESET      <= RX_SRESET_PIPE;
	 end 
   end 

   always @(posedge TX_FIFO_CLK or posedge COMB_SRESET_TX)
   begin
	 if (COMB_SRESET_TX == 1'b1)
	 begin
	   TX_FIFO_SRESET_PIPE <= 1'b1;
	   TX_FIFO_SRESET      <= 1'b1;
     end
	 else 
	 begin
	   TX_FIFO_SRESET_PIPE <= 1'b0;
	   TX_FIFO_SRESET      <= TX_FIFO_SRESET_PIPE;
	 end 
   end 

   always @(posedge RX_FIFO_CLK or posedge COMB_SRESET_RX)
   begin
	 if (COMB_SRESET_RX == 1'b1)
	 begin
	   RX_FIFO_SRESET_PIPE <= 1'b1;
	   RX_FIFO_SRESET      <= 1'b1;
     end
	 else 
	 begin
	   RX_FIFO_SRESET_PIPE <= 1'b0;
	   RX_FIFO_SRESET      <= RX_FIFO_SRESET_PIPE;
	 end 
   end 

   always @(posedge HOST_CLK or posedge RESET)
   begin
	 if (RESET == 1'b1)
	 begin
	   HOST_SRESET_PIPE <= 1'b1;
	   HOST_SRESET      <= 1'b1;
     end
	 else 
	 begin
	   HOST_SRESET_PIPE <= 1'b0;
	   HOST_SRESET      <= HOST_SRESET_PIPE;
	 end 
   end 

endmodule