configure.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

///////////////////////////////////////////////////////////////////////////////
//
//      Project:  1 Gig Ethernet MAC FIFO Reference Design
//      Version:  2.0
//      File   :  configure.v
//
//      Company:  Xilinx
// Contributors:  Xilinx Inc.
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// Management Configuration block for 1 Gig Ethernet MAC FIFO Reference Design
// Author: Xilinx Inc.
//
// Description: This is the configuration register block for the 1Gb/s MAC 
//		Backend.
//
//              Functionality:
//              1. The module address decodes the Address bus during a write 
//                 and takes data from the input data bus (WR_DATA).
//              2. The module address decodes the Address bus during a read and 
//                 drives data onto the output data bus (RD_DATA).
// 		3. The module contains the reset babysitting circuitry to 
//		   create four synchronous resets, one for each clock domain, 
//		   from the asynchronous reset.
// 
///////////////////////////////////////////////////////////////////////////////


`timescale 1 ps / 1 ps	

module CONFIGURE
  (HOST_CLK, 
   TX_FIFO_CLK, 
   RX_FIFO_CLK,                
   TX_CLK,                     
   RX_CLK,                     
   RESET,                      
   ADDR,                       
   RD_DATA,                    
   WR_DATA,                    
   W_R,                                             
   TX_NEARLY_EMPTY_THRESH,     
   TX_NEARLY_FULL_THRESH,      
   TX_SRESET_OUT,              
   RX_NEARLY_EMPTY_THRESH,     
   RX_NEARLY_FULL_HIGH_THRESH,
   RX_NEARLY_FULL_LOW_THRESH,  
   RX_SRESET_OUT,              
   PAUSE_VALUE,                
   PAUSE_REQ,                  
   FLOW_CTRL_EN,               
   TX_FIFO_SRESET_OUT,         
   RX_FIFO_SRESET_OUT);         
  
   parameter TX_FIFO_SIZE = 1024;   // FIFO size can be 512, 1034, 2048, 4096, 8192, 16384 words.
   parameter RX_FIFO_SIZE = 1024;   // FIFO size can be 512, 1034, 2048, 4096, 8192, 16384 words.
   
   // Other params used only internally...
   parameter log2_TX_FIFO_SIZE = (TX_FIFO_SIZE == 512 ? 9 : 
                                   (TX_FIFO_SIZE == 1024 ? 10 :
                                     (TX_FIFO_SIZE == 2048 ? 11 :
                                       (TX_FIFO_SIZE == 4096 ? 12 :
                                         (TX_FIFO_SIZE == 8192 ? 13 : 14)))));

   parameter log2_RX_FIFO_SIZE = (RX_FIFO_SIZE == 512 ? 9 : 
                                   (RX_FIFO_SIZE == 1024 ? 10 :
                                     (RX_FIFO_SIZE == 2048 ? 11 :
                                       (RX_FIFO_SIZE == 4096 ? 12 :
                                         (RX_FIFO_SIZE == 8192 ? 13 : 14)))));

   input HOST_CLK;                                           // The Host Clock.                              
   input TX_FIFO_CLK;                                        // The Transmitter FIFO clock.
   input RX_FIFO_CLK;                                        // The Receiver FIFO clock.
   input TX_CLK;                                             // MAC Transmitter clock.
   input RX_CLK;											 // MAC Receiver clock.
   input RESET;                                              // Global Asynchronous Reset.                              
   input [9:0] ADDR;                                         // Host Address bus.                                                     
   output [31:0] RD_DATA;                                    // Host output (read) data bus.                                                    
   input [31:0] WR_DATA;                                     // Host input (write) data bus.                                                    
   input W_R;                                                // Host Read/Write Strobe.
    
   output [log2_TX_FIFO_SIZE-1:0] TX_NEARLY_EMPTY_THRESH;     // TX_FIFO Nearly Empty Threshold.                                                                        
   output [log2_TX_FIFO_SIZE-1:0] TX_NEARLY_FULL_THRESH;      // TX_FIFO Nearly Full Threshold.                                                                        
   output TX_SRESET_OUT;									  // TX soft synchronous reset                                                            
   output [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_EMPTY_THRESH;     // RX_FIFO Nearly Empty Threshold.                                                                        
   output [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_FULL_HIGH_THRESH; // RX_FIFO Nearly Full High Threshold.                                                                        
   output [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_FULL_LOW_THRESH;  // RX_FIFO Nearly Full Low Threshold.                                                                        
   output RX_SRESET_OUT;									  // RX soft synchronous reset
   output [15:0] PAUSE_VALUE;                                 // Number of Pause Quanta for Pause.
   output PAUSE_REQ;                                          // "Manual" pause request.
   output FLOW_CTRL_EN;                                       // Enable "Automatic" pause requests.
   output TX_FIFO_SRESET_OUT;							      // TX_FIFO soft synchronous reset
   output RX_FIFO_SRESET_OUT;								  // RX_FIFO soft synchronous reset

   reg [log2_TX_FIFO_SIZE-1:0] TX_NEARLY_EMPTY_THRESHOLD;     // TX_FIFO Nearly Empty Threshold. 
   reg [log2_TX_FIFO_SIZE-1:0] TX_NEARLY_FULL_THRESHOLD;      // TX_FIFO Nearly Full Threshold. 
   reg [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_EMPTY_THRESHOLD;     // RX_FIFO Nearly Empty Threshold.
   reg [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_FULL_HIGH_THRESHOLD; // RX_FIFO Nearly Full High Threshold.
   reg [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_FULL_LOW_THRESHOLD;  // RX_FIFO Nearly Full Low Threshold.
   reg [log2_TX_FIFO_SIZE-1:0] TX_NEARLY_EMPTY_THRESH;     // TX_FIFO Nearly Empty Threshold.                                                                        
   reg [log2_TX_FIFO_SIZE-1:0] TX_NEARLY_FULL_THRESH;      // TX_FIFO Nearly Full Threshold.                                                                        
   reg [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_EMPTY_THRESH;     // RX_FIFO Nearly Empty Threshold.                                                                        
   reg [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_FULL_HIGH_THRESH; // RX_FIFO Nearly Full High Threshold.                                                                        
   reg [log2_RX_FIFO_SIZE-1:0] RX_NEARLY_FULL_LOW_THRESH;  // RX_FIFO Nearly Full Low Threshold.                                                                        
   reg [15:0] PAUSE_VALUE;                                 // Number of Pause Quanta for Pause.
   reg PAUSE_REQ;                                          // "Manual" pause request.
   reg FLOW_CTRL_EN;                                       // Enable "Automatic" pause requests.
   reg [31:0] RD_DATA;                                    // Host output (read) data bus.                                                    
   reg [15:0] PAUSE_TIME;                                    // Pause Quanta Periods of pause.     
   reg PAUSE_REQUEST;                                        // "Manual" pause request
   reg FLOW_CTRL_ENABLE;                                     // Enable "Automatic" pause requests.
   reg TX_RESET;										      // soft tx reset
   reg RX_RESET;										      // soft rx reset
   reg TX_SRESET;										      // sync reset
   reg RX_SRESET;
   reg TX_FIFO_SRESET;
   reg RX_FIFO_SRESET;
   reg HOST_SRESET;

   reg TX_SRESET_PIPE;										  // sync reset
   reg RX_SRESET_PIPE;
   reg TX_FIFO_SRESET_PIPE;
   reg RX_FIFO_SRESET_PIPE;
   reg HOST_SRESET_PIPE;

   assign TX_SRESET_OUT = TX_SRESET;
   assign RX_SRESET_OUT = RX_SRESET;
   assign TX_FIFO_SRESET_OUT = TX_FIFO_SRESET;
   assign RX_FIFO_SRESET_OUT = RX_FIFO_SRESET;
   
   wire COMB_RESET_TX;
   wire COMB_RESET_RX;
   wire COMB_SRESET_TX;
   wire COMB_SRESET_RX;

// purpose: Write Address Decoding 
// type   : sequential
   
   always @(posedge HOST_CLK)
   begin
     if(HOST_SRESET == 1'b1) 
     begin
       TX_NEARLY_EMPTY_THRESHOLD[log2_TX_FIFO_SIZE-1:4]     <= 0;
       TX_NEARLY_EMPTY_THRESHOLD[3:0]                       <= 4'b1111;
       TX_NEARLY_FULL_THRESHOLD[log2_TX_FIFO_SIZE-1:8]      <= 0;
       TX_NEARLY_FULL_THRESHOLD[7:0]                        <= 8'b11111111;
       RX_NEARLY_EMPTY_THRESHOLD[log2_RX_FIFO_SIZE-1:4]     <= 0;
       RX_NEARLY_EMPTY_THRESHOLD[3:0]                       <= 4'b1111;
       RX_NEARLY_FULL_HIGH_THRESHOLD[log2_RX_FIFO_SIZE-1:8] <= 0;
       RX_NEARLY_FULL_HIGH_THRESHOLD[7:0]                   <= 8'b11111111;
       RX_NEARLY_FULL_LOW_THRESHOLD[log2_RX_FIFO_SIZE-1:6]  <= 0;
       RX_NEARLY_FULL_LOW_THRESHOLD[5:0]                    <= 6'b111111;
       PAUSE_TIME                                           <= 16'h0000;
       PAUSE_REQUEST                                        <= 1'b0;
       FLOW_CTRL_ENABLE                                     <= 1'b1;
     end
     else
     begin
       PAUSE_REQUEST <= 1'b0; // reset PAUSE_REQUEST by default: it is only high when written high by Host I/F.
            
       if (W_R == 1'b0)
       begin
         case (ADDR[9:3])
            7'b1110000 : 
            begin
               TX_NEARLY_EMPTY_THRESHOLD     <= WR_DATA[log2_TX_FIFO_SIZE-1:0];
               TX_NEARLY_FULL_THRESHOLD      <= WR_DATA[log2_TX_FIFO_SIZE+15:16];
            end
            7'b1110001 : 
            begin
               RX_NEARLY_FULL_HIGH_THRESHOLD <= WR_DATA[log2_RX_FIFO_SIZE-1:0];
               RX_NEARLY_FULL_LOW_THRESHOLD  <= WR_DATA[log2_RX_FIFO_SIZE+15:16];
            end
            7'b1110010 :
               RX_NEARLY_EMPTY_THRESHOLD     <= WR_DATA[log2_RX_FIFO_SIZE-1:0];
            7'b1110011 :
            begin
               PAUSE_TIME                    <= WR_DATA[15:0];
               FLOW_CTRL_ENABLE              <= WR_DATA[16];
               PAUSE_REQUEST                 <= WR_DATA[17];          // send a "manual" pause request pulse.
            end
            default    : 
               ;
         endcase
       end
     end
   end

                                 

// purpose: Read Address Decoding 
// type   : sequential
   always @(posedge HOST_CLK)