gmac_rgmii_top.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

      .CE(1'b1), 
      .R(1'b0), 
      .S(1'b0) 
   );

   // Drive clock through Output Buffers and onto PADS.
      OBUF drive_rgmii_tx_clk     (.I(rgmii_tx_clk_obuf), .O(rgmii_tx_clk));

   ////////////////////////////////////////////////////////////////////////////
   // RGMII Transmitter Logic : drive TX signals through IOBs onto RGMII 
   // interface
   ////////////////////////////////////////////////////////////////////////////

   // IOB Output flip/flops.
   FDDRRSE rgmii_txd_ddr_0
     (
      .Q(rgmii_txd_obuf[0]),
      .D0(rgmii_txd_rising_int[0]),
      .D1(rgmii_txd_falling_int[0]),
      .C0(rgmii_tx_clk_int),
      .C1(not_rgmii_tx_clk_int),
      .CE(1'b1),
      .R(1'b0),
      .S(1'b0)
      );

   FDDRRSE rgmii_txd_ddr_1
     (
      .Q(rgmii_txd_obuf[1]),
      .D0(rgmii_txd_rising_int[1]),
      .D1(rgmii_txd_falling_int[1]),
      .C0(rgmii_tx_clk_int),
      .C1(not_rgmii_tx_clk_int),
      .CE(1'b1),
      .R(1'b0),
      .S(1'b0)
      );
      
   FDDRRSE rgmii_txd_ddr_2
     (
      .Q(rgmii_txd_obuf[2]),
      .D0(rgmii_txd_rising_int[2]),
      .D1(rgmii_txd_falling_int[2]),
      .C0(rgmii_tx_clk_int),
      .C1(not_rgmii_tx_clk_int),
      .CE(1'b1),
      .R(1'b0),
      .S(1'b0)
      );
      
   FDDRRSE rgmii_txd_ddr_3
     (
      .Q(rgmii_txd_obuf[3]),
      .D0(rgmii_txd_rising_int[3]),
      .D1(rgmii_txd_falling_int[3]),
      .C0(rgmii_tx_clk_int),
      .C1(not_rgmii_tx_clk_int),
      .CE(1'b1),
      .R(1'b0),
      .S(1'b0)
      );      
   
   // TX control signal
   FDDRRSE rgmii_tx_ctl_ddr
     (
      .Q(rgmii_tx_ctl_obuf),
      .D0(rgmii_tx_ctl_rising_int),
      .D1(rgmii_tx_ctl_falling_int),
      .C0(rgmii_tx_clk_int),
      .C1(not_rgmii_tx_clk_int),
      .CE(1'b1),
      .R(1'b0),
      .S(1'b0)
      );    

    //  drive RGMII Tx signals through Output Buffers and onto PADS.
    OBUF drive_rgmii_tx_ctl   (.I(rgmii_tx_ctl_obuf),    .O(rgmii_tx_ctl));

    OBUF drive_rgmii_txd3     (.I(rgmii_txd_obuf[3]),    .O(rgmii_txd[3]));
    OBUF drive_rgmii_txd2     (.I(rgmii_txd_obuf[2]),    .O(rgmii_txd[2]));
    OBUF drive_rgmii_txd1     (.I(rgmii_txd_obuf[1]),    .O(rgmii_txd[1]));
    OBUF drive_rgmii_txd0     (.I(rgmii_txd_obuf[0]),    .O(rgmii_txd[0]));

   ////////////////////////////////////////////////////////////////////////////
   // RGMII Receiver Clock Management : receive RX_CLK through IOBs from RGMII 
   // interface
   ////////////////////////////////////////////////////////////////////////////

   // Route gmii_rx_clk through an IBUFG and then through a BUFG (onto Global 
   // Clock Routing)
   IBUFG ibufg_rgmii_rx_clk   (.I(rgmii_rx_clk),       .O(rgmii_rx_clk_ibufg));
   BUFG  bufg_rgmii_rx_clk    (.I(rgmii_rx_clk_ibufg), .O(rgmii_rx_clk_bufg));

   INV invert_rgmii_rx_clk_int (.I(rgmii_rx_clk_int), .O(not_rgmii_rx_clk_int));
   
   assign rgmii_rx_clk_int = rgmii_rx_clk_bufg;

   ////////////////////////////////////////////////////////////////////////////
   // RGMII Receiver Logic : receive RX signals through IOBs from RGMII 
   // interface
   ////////////////////////////////////////////////////////////////////////////
   
    // Receive data DDRs
    IFDDRRSE rgmii_rxd0_ddr
    (
        .D(rgmii_rxd[0]),
        .Q0(rgmii_rxd_rising_int[0]),
        .Q1(rgmii_rxd_falling_int[0]),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );
    
    IFDDRRSE rgmii_rxd1_ddr
    (
        .D(rgmii_rxd[1]),
        .Q0(rgmii_rxd_rising_int[1]),
        .Q1(rgmii_rxd_falling_int[1]),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );
    
    IFDDRRSE rgmii_rxd2_ddr
    (
        .D(rgmii_rxd[2]),
        .Q0(rgmii_rxd_rising_int[2]),
        .Q1(rgmii_rxd_falling_int[2]),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );
    
    IFDDRRSE rgmii_rxd3_ddr
    (
        .D(rgmii_rxd[3]),
        .Q0(rgmii_rxd_rising_int[3]),
        .Q1(rgmii_rxd_falling_int[3]),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );


    // Transmit control DDR    
    IFDDRRSE rgmii_rx_ctl_ddr
    (
        .D(rgmii_rx_ctl),
        .Q0(rgmii_rx_ctl_rising_int),
        .Q1(rgmii_rx_ctl_falling_int),
        .C0(rgmii_rx_clk_int),
        .C1(not_rgmii_rx_clk_int),
        .CE(1'b1),
        .R(1'b0),
        .S(1'b0)
    );  

  /////////////////////////////////////////////////////////////////////////////
  // Instantiate the GMAC core
  /////////////////////////////////////////////////////////////////////////////
  GMAC_RGMII gmac_core 
     (
      // Reset signal
      .RESET(reset_int),
      
      // Client receiver interface
      .RX_CLK(rx_clk_int), 
      .RX_GOOD_FRAME(rx_good_frame_int), 
      .RX_BAD_FRAME(rx_bad_frame_int),
      .RX_DATA(rx_data_int), 
      .RX_DATA_VALID(rx_data_valid_int),
      .RX_STATISTICS_VECTOR(rx_statistics_vector_int),
      .RX_STATISTICS_VALID(rx_statistics_valid_int),
      
      // Client transmitter interface
      .TX_CLK(tx_clk_int), 
      .TX_DATA(tx_data_int), 
      .TX_DATA_VALID(tx_data_valid_int),
      .TX_UNDERRUN(tx_underrun_int), 
      .TX_ACK(tx_ack_int), 
      .TX_RETRANSMIT(tx_retransmit_int), 
      .TX_COLLISION(tx_collision_int),
      .TX_IFG_DELAY(tx_ifg_delay_int),
      .TX_STATISTICS_VECTOR(tx_statistics_vector_int),
      .TX_STATISTICS_VALID(tx_statistics_valid_int),
      
      // MAC control interface
      .PAUSE_REQ(pause_req_int), 
      .PAUSE_VAL(pause_val_int),
      
      // RGMII interface
      .GTX_CLK(gtx_clk_bufg),       
      .RGMII_TX_CTL_RISING(rgmii_tx_ctl_rising_int),
      .RGMII_TX_CTL_FALLING(rgmii_tx_ctl_falling_int),      
      .RGMII_TXD_RISING(rgmii_txd_rising_int),
      .RGMII_TXD_FALLING(rgmii_txd_falling_int),   
      .RGMII_TX_CLK(rgmii_tx_clk_int),   
      .RGMII_RX_CTL_RISING(rgmii_rx_ctl_rising_int),
      .RGMII_RX_CTL_FALLING(rgmii_rx_ctl_falling_int),
      .RGMII_RXD_RISING(rgmii_rxd_rising_int),
      .RGMII_RXD_FALLING(rgmii_rxd_falling_int),            
      .RGMII_RX_CLK(rgmii_rx_clk_int),
      .RGMII_RX_SPEED(rgmii_rx_speed),
      .RGMII_RX_DUPLEX(rgmii_rx_duplex),
      .RGMII_LINK(rgmii_link),
      
      // MDIO interface
      .MDIO_IN(mdio_in_int), 
      .MDIO_OUT(mdio_out_int), 
      .MDIO_TRI(mdio_tri_int), 
      .MDC(mdc_int),
      
      // HOST interface
      .HOST_CLK(host_clk_bufg), 
      .HOST_OPCODE(host_opcode_int),
      .HOST_ADDR(host_addr_int), 
      .HOST_WR_DATA(host_wr_data_int), 
      .HOST_REQ(host_req_int), 
      .HOST_MIIM_SEL(host_miim_sel_int),
      .HOST_RD_DATA(host_rd_data_int), 
      .HOST_MIIM_RDY(host_miim_rdy_int)
);


  /////////////////////////////////////////////////////////////////////////////
  // All of the following signals are the clients connections to the core.  
  // These are designed to be internal connections within the FPGA fabric.  
  // IOB's are placed on these only for the purpose of allowing the core (as a 
  // standalone design) to be implemented as an example in an FPGA device.
  // In addition, the STATISTICS_VECTOR and STATISTICS_VALID signals are 
  // registered to help with timing issues assoicated with IOB usage.
  /////////////////////////////////////////////////////////////////////////////


   IBUF reset_i   (.I(reset), .O(reset_int));
                         
   OBUF rx_clk_o   (.I(rx_clk_int), .O(rx_clk));
                 
   OBUF rx_good_frame_o   (.I(rx_good_frame_int), .O(rx_good_frame));
          
   OBUF rx_bad_frame_o    (.I(rx_bad_frame_int), .O(rx_bad_frame));
           
   OBUF rx_data_o7  (.I(rx_data_int[7]), .O(rx_data[7]));            
   OBUF rx_data_o6  (.I(rx_data_int[6]), .O(rx_data[6]));            
   OBUF rx_data_o5  (.I(rx_data_int[5]), .O(rx_data[5]));            
   OBUF rx_data_o4  (.I(rx_data_int[4]), .O(rx_data[4]));            
   OBUF rx_data_o3  (.I(rx_data_int[3]), .O(rx_data[3]));            
   OBUF rx_data_o2  (.I(rx_data_int[2]), .O(rx_data[2]));            
   OBUF rx_data_o1  (.I(rx_data_int[1]), .O(rx_data[1]));            
   OBUF rx_data_o0  (.I(rx_data_int[0]), .O(rx_data[0]));
     
   OBUF rx_data_valid_o   (.I(rx_data_valid_int), .O(rx_data_valid));            
                  
   always @ (posedge rx_clk_int or posedge reset_int )
      begin
        if (reset_int)
           begin		 
              rx_statistics_valid_reg <= 1'b0;
			  rx_statistics_vector_reg <= 23'b0;
           end
        else
           begin		 
              rx_statistics_valid_reg <= rx_statistics_valid_int;
			  rx_statistics_vector_reg <= rx_statistics_vector_int;
           end
      end
          
   OBUF rx_statistics_vector_o22  (.I(rx_statistics_vector_reg[22]), 
                                   .O(rx_statistics_vector[22]));