gmac_rgmii_top.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

///////////////////////////////////////////////////////////////////////////////
//
//      Project:  RGMII/Gigabit Ethernet MAC
//      Version:  1.0
//      File   :  gmac_rgmii_top.v
//
//      Company:  Xilinx
// Contributors:  Ting Kao, Mary Low
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// RGMII Gigabit Ethernet MAC Wrapper
// Author: Ting Kao
// Translated to Verilog by Mary Low
//
// Description: This is the wrapper that instantiates the RGMII GMAC module
//              with the clocking scheme and IOBs.
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1 ps	 

module GMAC_RGMII_TOP
(
    reset,                   
    /////////////////////////////////////////////////////////////////////////
    // Client Receiver Interface
    /////////////////////////////////////////////////////////////////////////
    rx_clk,               
    rx_good_frame,        
    rx_bad_frame,         
    rx_data,              
    rx_data_valid,        
    rx_statistics_vector, 
    rx_statistics_valid,  
    /////////////////////////////////////////////////////////////////////////
    // Client Transmitter Interface
    /////////////////////////////////////////////////////////////////////////
    tx_clk,               
    tx_data,              
    tx_data_valid,        
    tx_underrun,          
    tx_ack,               
    tx_retransmit,        
    tx_collision,         
    tx_ifg_delay,         
    tx_statistics_vector, 
    tx_statistics_valid,  
    /////////////////////////////////////////////////////////////////////////
    // GMAC Control Interface
    /////////////////////////////////////////////////////////////////////////
    pause_req,            
    pause_val,             
    /////////////////////////////////////////////////////////////////////////
    // RGMII Interface
    /////////////////////////////////////////////////////////////////////////
    gtx_clk,                  
    rgmii_txd,              
    rgmii_tx_ctl,           
    rgmii_tx_clk,          
    rgmii_rxd,              
    rgmii_rx_ctl,
    rgmii_rx_clk,	   
	   
    /////////////////////////////////////////////////////////////////////////
    // MDIO Interface
    /////////////////////////////////////////////////////////////////////////
    mdio_in,                  
    mdio_out,                 
    mdio_tri,                 
    mdc,	   
    /////////////////////////////////////////////////////////////////////////
    // Host Interface
    /////////////////////////////////////////////////////////////////////////
    host_clk,            
    host_opcode,          
    host_addr,           
    host_wr_data,          
    host_req,            
    host_miim_sel,       
    host_rd_data,          
    host_miim_rdy
 );


   /////////////////////////////////////////////////////////////////////////
   // Port declarations
   /////////////////////////////////////////////////////////////////////////   
   input          reset;                   
   /////////////////////////////////////////////////////////////////////////
   // Client Receiver Interface
   /////////////////////////////////////////////////////////////////////////
   output         rx_clk;               
   output         rx_good_frame;        
   output         rx_bad_frame;         
   output [7:0]   rx_data;              
   output         rx_data_valid;        
   output [22:0]  rx_statistics_vector; 
   output	  rx_statistics_valid;  
   /////////////////////////////////////////////////////////////////////////
   // Client Transmitter Interface
   /////////////////////////////////////////////////////////////////////////
   output         tx_clk;               
   input  [7:0]   tx_data;               
   input          tx_data_valid;        
   input          tx_underrun;          
   output         tx_ack;               
   output         tx_retransmit;        
   output         tx_collision;         
   input  [7:0]   tx_ifg_delay;         
   output [28:0]  tx_statistics_vector; 
   output	  tx_statistics_valid;  
   /////////////////////////////////////////////////////////////////////////
   // GMAC Control Interface
   /////////////////////////////////////////////////////////////////////////
   input          pause_req;            
   input  [15:0]  pause_val;            
   /////////////////////////////////////////////////////////////////////////
   // RGMII Interface
   /////////////////////////////////////////////////////////////////////////
   input          gtx_clk;                                   
   output [3:0]   rgmii_txd;             
   output         rgmii_tx_ctl;                      
   output         rgmii_tx_clk;          
   input  [3:0]   rgmii_rxd;             
   input          rgmii_rx_ctl;                             
   input          rgmii_rx_clk;                     
                     
   /////////////////////////////////////////////////////////////////////////
   // MDIO Interface
   /////////////////////////////////////////////////////////////////////////
   input          mdio_in;                  
   output         mdio_out;                 
   output         mdio_tri;                 
   output         mdc;                     
   /////////////////////////////////////////////////////////////////////////
   // Host Interface
   /////////////////////////////////////////////////////////////////////////
   input          host_clk;             
   input  [1:0]   host_opcode;           
   input  [9:0]   host_addr;            
   input  [31:0]  host_wr_data;           
   input          host_req;             
   input          host_miim_sel;        
   output [31:0]  host_rd_data;           
   output         host_miim_rdy;

   ////////////////////////////////////////////////////////////////////////////
   // internal signals used in this top level wrapper.
   ////////////////////////////////////////////////////////////////////////////
   wire         host_clk_ibufg;       // host_clk routed through an IBUFG
   wire         host_clk_bufg;        // host_clk_ibufg routed through a 
   				      //  BUFG: onto Global Clock Routing
   wire         gtx_clk_ibufg;        // gtx_clk routed through an IBUFG
   wire         gtx_clk_bufg;         // gtx_clk_ibufg routed through a 
   				      //  BUFG: onto Global Clock Routing
   
   wire         gmii_tx_clk_int;      // Internal gmii_tx_clk 
   wire         not_gmii_tx_clk_int;  // gmii_tx_clk_int routed through an 
   				      //  inverter   

   wire [3:0]   rgmii_txd_rising_int; 
   wire [3:0]   rgmii_txd_falling_int;
   wire [3:0]   rgmii_txd_obuf;
   wire         rgmii_tx_ctl_rising_int;
   wire         rgmii_tx_ctl_falling_int;
   wire         rgmii_tx_ctl_obuf;
   wire	        not_rgmii_tx_clk_int;
   wire		rgmii_tx_clk_obuf;
   
   wire         rgmii_rx_clk_ibufg;
   wire         rgmii_rx_clk_bufg;
   wire         rgmii_rx_clk_int;
   wire         not_rgmii_rx_clk_int;
   
   wire [3:0]   rgmii_rxd_rising_int;
   wire [3:0]   rgmii_rxd_falling_int;
   wire         rgmii_rx_ctl_rising_int;
   wire         rgmii_rx_ctl_falling_int;
   wire [1:0]   rgmii_rx_speed;
   
   wire         reset_int;   
   wire         rx_clk_int;    
   wire         rx_good_frame_int;    
   wire         rx_bad_frame_int;    
   wire [7:0]   rx_data_int; 
   wire         rx_data_valid_int;    
   wire [22:0]  rx_statistics_vector_int;
   wire         rx_statistics_valid_int;
   wire         tx_clk_int;    
   wire [7:0]   tx_data_int;  
   wire         tx_data_valid_int;    
   wire         tx_underrun_int;    
   wire         tx_ack_int;    
   wire         tx_retransmit_int;    
   wire         tx_collision_int;    
   wire [7:0]   tx_ifg_delay_int;
   wire [28:0]  tx_statistics_vector_int;
   wire         tx_statistics_valid_int;
   wire         pause_req_int;    
   wire [15:0]  pause_val_int;
   
   reg [22:0]   rx_statistics_vector_reg;
   reg          rx_statistics_valid_reg;
   reg [28:0]   tx_statistics_vector_reg;
   reg          tx_statistics_valid_reg;
    
        
   wire         mdio_in_int;    
   wire         mdio_out_int;    
   wire         mdio_tri_int;    
   wire         mdc_int;    
   wire         host_clk_int;   
   wire [1:0]   host_opcode_int;  
   wire [9:0]   host_addr_int; 
   wire [31:0]  host_wr_data_int;  
   wire         host_req_int;   
   wire         host_miim_sel_int;  
   wire [31:0]  host_rd_data_int;  
   wire         host_miim_rdy_int;
  

   ////////////////////////////////////////////////////////////////////////////
   // HOST Clock Management
   ////////////////////////////////////////////////////////////////////////////
   // The following instance of a clock buffer should be added if one is not
   // provided elsewhere in your design. Remember to add the signal 
   // declarations and rename the signal in the core port map.
   IBUFG ibufg_host_clk   (.I(host_clk),              .O(host_clk_ibufg));
   BUFG  bufg_host_clk    (.I(host_clk_ibufg),        .O(host_clk_bufg));
   ////////////////////////////////////////////////////////////////////////////
   // gtx_clk Clock Management
   ////////////////////////////////////////////////////////////////////////////

   // Route gtx_clk through an IBUFG and then through a BUFG (onto Global Clock 
   // Routing)
   IBUFG ibufg_gtx_clk       (.I(gtx_clk),               .O(gtx_clk_ibufg));
   BUFG  bufg_gtx_clk        (.I(gtx_clk_ibufg),         .O(gtx_clk_bufg));

   ////////////////////////////////////////////////////////////////////////////
   // RGMII Transmitter Clock Management : drive rgmii_tx_clk through IOB onto 
   // RGMII interface
   ////////////////////////////////////////////////////////////////////////////

   // Invert rgmii_tx_clk
   INV invert_rgmii_tx_clk_int (.I(rgmii_tx_clk_int), .O(not_rgmii_tx_clk_int));

   // Instantiate a DDR output register.  This is a good way to drive 
   // rgmii_tx_clk since the clock-to-PAD delay will be the same as that for 
   // data driven from IOB Ouput flip-flops eg rgmii_txd[3:0].  
   FDDRRSE rgmii_tx_clk_ddr (
      .Q(rgmii_tx_clk_obuf), 
      .D0(1'b1),
      .D1(1'b0),
      .C0(rgmii_tx_clk_int),
      .C1(not_rgmii_tx_clk_int),