📄 hardware.lst
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.DEFINE C_D2_LatchA 0x0020 //
.DEFINE C_D2_LatchB 0x0040 //
.DEFINE C_D2_LatchAB 0x00C0 //
//... Define for P_LVD_Ctrl ...................
.DEFINE C_LVD24V 0x0000 // LVD = 2.4V
.DEFINE C_LVD28V 0x0001 // LVD = 2.8V
.DEFINE C_LVD32V 0x0002 // LVD = 3.2V
.DEFINE C_LVD36V 0x0003 // LVD = 3.6V
/////////////////////////////////////////////////////////////////
// Note: This register map to the P_INT_Ctrl(0x7010)
// User's interrupt setting have to combine with this register
// while co-work with SACM library.
//
// See. following function for example:
// F_SP_SACM_A2000_Init_:
// F_SP_SACM_S480_Init_:
// F_SP_SACM_S240_Init_:
// F_SP_SACM_MS01_Init_:
// F_SP_SACM_DVR_Init_:
//////////////////////////////////////////////////
0000049B .IRAM
0000049B 00 00 .VAR R_InterruptStatus = 0 //
//////////////////////////////////////////////////
.define C_RampDelayTime 16
.define C_QueueSize 100
0000049C 00 00 .VAR R_Queue
0000049D 00 00 00 00 .DW C_QueueSize-1 DUP(0)
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00
00000500 00 00 .VAR R_ReadIndex
00000501 00 00 .VAR R_WriteIndex
0000BBFF .CODE
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,R2
///////////////////////////////////////////
_SP_InitQueue: .PROC
_SP_InitQueue_A2000:
_SP_InitQueue_S480:
_SP_InitQueue_S240:
_SP_InitQueue_MS01:
_SP_InitQueue_DVR:
F_SP_InitQueue_A2000:
F_SP_InitQueue_S480:
F_SP_InitQueue_S240:
F_SP_InitQueue_MS01:
F_SP_InitQueue_DVR:
F_SP_InitQueue:
0000BBFF 09 93 9C 04 R1 = R_Queue
0000BC01 40 94 R2 = 0
L_ClearQueueLoop?:
0000BC02 D1 D4 [R1++] = R2
0000BC03 09 43 00 05 cmp R1, R_Queue+C_QueueSize
0000BC05 44 4E jne L_ClearQueueLoop?
0000BC06 40 92 R1 = 0
0000BC07 19 D3 00 05 [R_ReadIndex] = R1
0000BC09 19 D3 01 05 [R_WriteIndex] = R1
0000BC0B 90 9A RETF
.ENDP
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_A2000:
F_SP_ReadQueue_S480:
F_SP_ReadQueue_S240:
F_SP_ReadQueue_MS01:
F_SP_ReadQueue_DVR:
F_SP_ReadQueue:
0000BC0C 12 95 00 05 R2 = [R_ReadIndex]
0000BC0E 12 45 01 05 cmp R2,[R_WriteIndex]
0000BC10 0D 5E je L_RQ_QueueEmpty
0000BC11 0A 05 9C 04 R2 += R_Queue // get queue data address
0000BC13 C2 92 R1 = [R2]
0000BC14 12 95 00 05 R2 = [R_ReadIndex]
0000BC16 41 04 R2 += 1
0000BC17 0A 45 64 00 cmp R2, C_QueueSize
0000BC19 01 4E jne L_RQ_NotQueueBottom
0000BC1A 40 94 R2 = 0
L_RQ_NotQueueBottom:
0000BC1B 1A D5 00 05 [R_ReadIndex] = R2
//r2 = 0x0000 // get queue data
0000BC1D 90 9A retf
L_RQ_QueueEmpty:
//r2 = 0x8000 // queue empty
0000BC1E 90 9A retf
///////////////////////////////////////////
// Function: Get a data from Queue but do
// not change queue index
// R1: output
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_NIC:
F_SP_ReadQueue_NIC_A2000:
F_SP_ReadQueue_NIC_S480:
F_SP_ReadQueue_NIC_S240:
F_SP_ReadQueue_NIC_MS01:
F_SP_ReadQueue_NIC_DVR:
0000BC1F 12 95 00 05 R2 = [R_ReadIndex]
0000BC21 12 45 01 05 cmp R2,[R_WriteIndex]
0000BC23 03 5E je L_RQ_QueueEmpty?
0000BC24 0A 05 9C 04 R2 += R_Queue // get queue data index
0000BC26 C2 92 R1 = [R2]
L_RQ_QueueEmpty?:
0000BC27 90 9A RETF
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2
///////////////////////////////////////////
F_SP_WriteQueue_A2000:
F_SP_WriteQueue_S480:
F_SP_WriteQueue_S240:
F_SP_WriteQueue_MS01:
F_SP_WriteQueue_DVR:
F_SP_WriteQueue:
0000BC28 12 95 01 05 R2 = [R_WriteIndex] // put data to queue
0000BC2A 0A 05 9C 04 R2 += R_Queue
0000BC2C C2 D2 [R2] = R1
0000BC2D 12 95 01 05 R2 = [R_WriteIndex]
0000BC2F 41 04 R2 += 1
0000BC30 0A 45 64 00 cmp R2, C_QueueSize
0000BC32 01 4E jne L_WQ_NotQueueBottom
0000BC33 40 94 R2 = 0
L_WQ_NotQueueBottom:
0000BC34 1A D5 01 05 [R_WriteIndex] = R2
0000BC36 90 9A RETF
///////////////////////////////////////////
// Function: Test Queue Status
// o/p: R1
// Destory: R1
///////////////////////////////////////////
F_SP_TestQueue_A2000:
F_SP_TestQueue_S480:
F_SP_TestQueue_S240:
F_SP_TestQueue_MS01:
F_SP_TestQueue_DVR:
F_SP_TestQueue:
//... Test Queue Empty ...
0000BC37 11 93 00 05 R1 = [R_ReadIndex]
0000BC39 11 43 01 05 cmp R1,[R_WriteIndex]
0000BC3B 12 5E je L_TQ_QueueEmpty
//... Test Queue Full ...
0000BC3C 11 93 00 05 R1 = [R_ReadIndex] // For N Queue Full: 1.R=0 and W=N-1 2. R<>0 and W=R-1
0000BC3E 05 4E jnz L_TQ_JudgeCond2
0000BC3F 11 93 01 05 R1 = [R_WriteIndex]
0000BC41 09 43 63 00 cmp R1, C_QueueSize-1 // Cond1
0000BC43 08 5E je L_TQ_QueueFull
L_TQ_JudgeCond2:
0000BC44 11 93 00 05 R1 = [R_ReadIndex]
0000BC46 41 22 R1 -=1
0000BC47 11 43 01 05 cmp R1,[R_WriteIndex]
0000BC49 02 5E je L_TQ_QueueFull
0000BC4A 40 92 r1 = 0 // not Full, not empty
0000BC4B 90 9A retf
L_TQ_QueueFull:
0000BC4C 41 92 r1 = 1 // full
0000BC4D 90 9A retf
L_TQ_QueueEmpty:
0000BC4E 42 92 r1 = 2 // empty
0000BC4F 90 9A retf
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_A2000_Initial()
// or F_SACM_A2000_Initial:
// Note: The following functions are the partial code of original
// initial subroutine. (H/W setting part)
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