qpsk_mod_const_freq.mdl

QPSK发送机

"led and held on positve edge)"
		    axes6		    "registered odd data stream (sampl"
"ed and held on negaitve edge)"
		    axes7		    "registered odd data stream (re-re"
"gistered on positive edge)"
		  }
		  YMin			  "-5~-5~-5~-5~-5~-5~-5"
		  YMax			  "5~5~5~5~5~5~5"
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		  Location		  [1, 50, 1025, 737]
		  Open			  off
		  NumInputPorts		  "7"
		  List {
		    ListType		    AxesTitles
		    axes1		    "clock"
		    axes2		    "serial data"
		    axes3		    "even data stream"
		    axes4		    "odd data stream"
		    axes5		    "registered even data stream (samp"
"led and held on negaitve edge)"
		    axes6		    "registered even data stream (re-r"
"egistered on positive edge) "
		    axes7		    "registered odd data stream (sampl"
"ed and held on positve edge)"
		  }
		  TimeRange		  "10"
		  YMin			  "-5~-5~-5~-5~-5~-5~-5"
		  YMax			  "5~5~5~5~5~5~5"
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		  BlockType		  Outport
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		  IconDisplay		  "Port number"
		  BusOutputAsStruct	  off
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		Block {
		  BlockType		  Outport
		  Name			  "even bit stream"
		  Position		  [935, 293, 965, 307]
		  Port			  "2"
		  IconDisplay		  "Port number"
		  BusOutputAsStruct	  off
		}
		Line {
		  SrcBlock		  "In1"
		  SrcPort		  1
		  Points		  [20, 0]
		  Branch {
		    DstBlock		    "Data Type Conversion1"
		    DstPort		    1
		  }
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		    Points		    [0, -125]
		    DstBlock		    "ser_to_prll"
		    DstPort		    2
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		Line {
		  SrcBlock		  "In2"
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		  Points		  [15, 0]
		  Branch {
		    DstBlock		    "Data Type Conversion"
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		  }
		  Branch {
		    Points		    [0, -210]
		    DstBlock		    "ser_to_prll"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "NOT gate"
		  SrcPort		  1
		  Points		  [25, 0; 0, -5]
		  Branch {
		    Points		    [0, -45]
		    DstBlock		    "Logical\nOperator"
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		  Branch {
		    Points		    [0, 220; 210, 0; 0, -145]
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		}
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		  SrcBlock		  "Data Type Conversion1"
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		  Points		  [0, 0; 90, 0]
		  Branch {
		    DstBlock		    "Logical\nOperator"
		    DstPort		    1
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		  Branch {
		    Points		    [0, 100]
		    DstBlock		    "Logical\nOperator1"
		    DstPort		    1
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		  SrcBlock		  "Logical\nOperator"
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		  Points		  [40, 0]
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		    Points		    [0, -215]
		    DstBlock		    "ser_to_prll"
		    DstPort		    3
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		  SrcBlock		  "Data Type Conversion"
		  SrcPort		  1
		  Points		  [0, 0; 5, 0]
		  Branch {
		    DstBlock		    "NOT gate"
		    DstPort		    1
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		  Branch {
		    Points		    [0, 45]
		    Branch {
		    Points		    [0, 5]
		    DstBlock		    "Logical\nOperator1"
		    DstPort		    2
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		    Branch {
		    Points		    [0, 205; 290, 0; 0, -60]
		    Branch {
		    DstBlock		    "D Flip-Flop"
		    DstPort		    2
		    }
		    Branch {
		    Points		    [0, 60; 155, 0; 0, -175]
		    DstBlock		    "D Flip-Flop2"
		    DstPort		    2
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		    }
		  }
		}
		Line {
		  SrcBlock		  "D Flip-Flop"
		  SrcPort		  1
		  Points		  [265, 0]
		  Branch {
		    DstBlock		    "odd bit stream"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, -40]
		    DstBlock		    "ser_to_prll"
		    DstPort		    7
		  }
		}
		Line {
		  SrcBlock		  "Constant1"
		  SrcPort		  1
		  DstBlock		  "D Flip-Flop1"
		  DstPort		  3
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "D Flip-Flop"
		  DstPort		  3
		}
		Line {
		  SrcBlock		  "Constant2"
		  SrcPort		  1
		  DstBlock		  "D Flip-Flop2"
		  DstPort		  3
		}
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		  SrcBlock		  "D Flip-Flop2"
		  SrcPort		  1
		  Points		  [5, 0]
		  Branch {
		    DstBlock		    "even bit stream"
		    DstPort		    1
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		    Points		    [0, -165]
		    DstBlock		    "ser_to_prll"
		    DstPort		    6
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		  SrcBlock		  "D Flip-Flop1"
		  SrcPort		  1
		  Points		  [45, 0]
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		    DstBlock		    "D Flip-Flop2"
		    DstPort		    1
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		  Branch {
		    Points		    [5, 0; 0, -180]
		    DstBlock		    "ser_to_prll"
		    DstPort		    5
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		}
		Annotation {
		  Name			  "data type convertor required \nconv"
"ert bit type into boolean\n"
		  Position		  [71, 139]
		  ForegroundColor	  "red"
		  BackgroundColor	  "yellow"
		}
		Annotation {
		  Name			  "NOT gate \nimplemented \nusing trut"
"h table"
		  Position		  [231, 324]
		  ForegroundColor	  "red"
		  BackgroundColor	  "yellow"
		}
		Annotation {
		  Name			  "DFF used to hold \nbits constant fo"
"r \ntwo bit periods"
		  Position		  [606, 239]
		  ForegroundColor	  "red"
		  BackgroundColor	  "yellow"
		}
		Annotation {
		  Name			  "Both outputs are \nregistered at th"
"e \nsame clock edge\nto align the two \ndata streams\n"
		  Position		  [946, 99]
		  ForegroundColor	  "red"
		  BackgroundColor	  "yellow"
		  FontName		  "Arial"
		  FontSize		  12
		  FontWeight		  "bold"
		}
		Annotation {
		  Name			  "Serial data is \ndenultiplexed and "
"\ndemultiplexed data \nstreams are registered\n\nTwo AND gates \nwith a NOT g"
"ate \nform a DEMUX "
		  Position		  [361, 389]
		  ForegroundColor	  "red"
		  BackgroundColor	  "yellow"
		}
		Annotation {
		  Name			  "even bit stream first registered \n"
"on negative edge and then on \npositive edge to allign \nwith the odd bit str"
"eam"
		  Position		  [731, 409]
		  ForegroundColor	  "red"
		  BackgroundColor	  "yellow"
		}
		Annotation {
		  Name			  "odd bit sream is \nregistered only "
"once \nin positive edge"
		  Position		  [496, 144]
		  ForegroundColor	  "red"
		  BackgroundColor	  "yellow"
		}
	      }
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "even_out"
	      Position		      [490, 278, 520, 292]
	      IconDisplay	      "Port number"
	      BusOutputAsStruct	      off
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "odd_out"
	      Position		      [490, 148, 520, 162]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      BusOutputAsStruct	      off
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "data_ser"
	      Position		      [175, 18, 205, 32]
	      Port		      "3"
	      IconDisplay	      "Port number"
	      BusOutputAsStruct	      off
	    }
	    Line {
	      SrcBlock		      "ser_prll"
	      SrcPort		      2
	      Points		      [15, 0]
	      Branch {
		DstBlock		"even_out"
		DstPort			1
	      }
	      Branch {
		Points			[0, -195]
		DstBlock		"Scope"
		DstPort			3
	      }
	    }
	    Line {
	      SrcBlock		      "clock\nsource"
	      SrcPort		      1
	      Points		      [80, 0]
	      Branch {
		DstBlock		"ser_prll"
		DstPort			2
	      }
	      Branch {
		Points			[0, -235]
		DstBlock		"Scope"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "ser_prll"
	      SrcPort		      1
	      Points		      [50, 0]
	      Branch {
		DstBlock		"odd_out"
		DstPort			1
	      }
	      Branch {
		Points			[0, -45]
		DstBlock		"Scope"
		DstPort			4
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	    }
	    Line {
	      SrcBlock		      "data source"
	      SrcPort		      1
	      Points		      [35, 0]
	      Branch {
		Points			[0, -130]
		DstBlock		"data_ser"
		DstPort			1
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	      Branch {
		Points			[45, 0]
		Branch {
		  DstBlock		  "ser_prll"
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		  Points		  [0, -85]
		  DstBlock		  "Scope"
		  DstPort		  2
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	      }
	    }
	    Annotation {
	      Name		      "bit period of the data \nis equal to ha"
"lf the \nclock period\n"
	      Position		      [71, 104]
	      ForegroundColor	      "red"
	      BackgroundColor	      "yellow"
	    }
	    Annotation {
	      Name		      "clock is used as both \nthe triger for "
"D-flop and \nselector signal for the \ndemultiplexor"
	      Position		      [66, 354]
	      ForegroundColor	      "red"
	      BackgroundColor	      "yellow"
	    }
	    Annotation {
	      Name		      "registered parallel data \nappears one "
"clock later"
	      Position		      [606, 84]
	      ForegroundColor	      "red"
	      BackgroundColor	      "yellow"
	    }
	  }
	}
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	  Position		  [710, 494, 740, 526]
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	  ZoomMode		  "xonly"
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	  Phase			  "pi"
	  SampleTime		  "0.001"
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	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  System {
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	    ModelBrowserWidth	    200
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	    Block {
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