📄 deftyp.h
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#ifndef _deftyp.h
#define _deftyp.h
#include "incldef.h"
struct UARTmode_info
{
int UARTmode_code;
const char * UARTmode_name;
};
static const UARTmode_info gUARTmodes[] = {
{0x00, "i8250"}, // Original ACE UART
{0x01, "c450"}, // Improved UART, No FIFO
{0x02, "c550"}, // Working 16 byte FIFO
{0x03, "E550"}, // Working 128 byte FIFO
{0x04, "c650"}, // 128 byte FIFO
{0x05, "c750"}, // 128 byte FIFO
{0x06, "c950"}, // 128 byte FIFO
{0x80, "other"} // Unknown UART
};
struct UARTportAddr_info
{
int portaddr ;
const char *UARTport_no ;
};
static const UARTportAddr_info PortAddroffset[] =
{
{ 0x00, "UART0" },
{ 0x08, "UART1" },
{ 0x10, "UART2" },
{ 0x18, "UART3" },
{0x800, "UART4" },
{0x808, "UART5" },
{0x810, "UART6" },
{0x818, "UART7" }
};
struct BautRateDivisor_info
{
unsigned int DLM;
unsigned int DLL;
const char *bautrate;
};
static const BautRateDivisor_info StandBRDiv[] =
{
{ 0x09,0x00, "br50" },
{ 0x03,0x00, "br110" },
{ 0x01,0x80, "br300" },
{ 0x00,0xc0, "br600" },
{ 0x00,0x60, "br1200" },
{ 0x00,0x30, "br2400" },
{ 0x00,0x18, "br4800" },
{ 0x00,0x0c, "br9600" },
{ 0x00,0x06, "br19200" },
{ 0x00,0x04, "br28800" },
{ 0x00,0x03, "br38400" },
{ 0x00,0x02, "br57600" },
{ 0x00,0x01, "br115200" }
};
static const unsigned int portadr[] =
{0x00,0x08,0x10,0x18,0x800,0x808,0x810,0x818};
struct testmode_info
{
const char *testmodes;
int testmodeval;
};
static const testmode_info testmodeset[] =
{
{"tm1" ,1}, /*Int Serch Gets */
{"tm2" ,2}, /*I*/
{"tm3" ,3}, /*I G*/
{"tm4" ,4}, /*I S*/
{"tm5" ,5}, /*S*/
{"tm6" ,6}, /*G S*/
{"tm7" ,7} /*G*/
};
/************************************************************************/
/* Types */
/************************************************************************/
typedef unsigned char BYTE ;
typedef unsigned short WORD ;
typedef unsigned long DWORD ;
//----------------------------------------------------------------------
struct PCIcfg
{
WORD vendorID ;
WORD deviceID ;
WORD command_reg ;
WORD status_reg ;
BYTE revisionID ;
BYTE progIF ;
BYTE subclass ;
BYTE classcode ;
BYTE cacheline_size ;
BYTE latency ;
BYTE header_type ;
BYTE BIST ;
union
{
struct
{
DWORD base_address0 ;
DWORD base_address1 ;
DWORD base_address2 ;
DWORD base_address3 ;
DWORD base_address4 ;
DWORD base_address5 ;
DWORD CardBus_CIS ;
WORD subsystem_vendorID ;
WORD subsystem_deviceID ;
DWORD expansion_ROM ;
BYTE cap_ptr ;
BYTE reserved1[3] ;
DWORD reserved2[1] ;
BYTE interrupt_line ;
BYTE interrupt_pin ;
BYTE min_grant ;
BYTE max_latency ;
DWORD device_specific[48] ;
} nonbridge ;
struct
{
DWORD base_address0 ;
DWORD base_address1 ;
BYTE primary_bus ;
BYTE secondary_bus ;
BYTE subordinate_bus ;
BYTE secondary_latency ;
BYTE IO_base_low ;
BYTE IO_limit_low ;
WORD secondary_status ;
WORD memory_base_low ;
WORD memory_limit_low ;
WORD prefetch_base_low ;
WORD prefetch_limit_low ;
DWORD prefetch_base_high ;
DWORD prefetch_limit_high ;
WORD IO_base_high ;
WORD IO_limit_high ;
DWORD reserved2[1] ;
DWORD expansion_ROM ;
BYTE interrupt_line ;
BYTE interrupt_pin ;
WORD bridge_control ;
DWORD device_specific[48] ;
} bridge ;
struct
{
DWORD ExCa_base ;
BYTE cap_ptr ;
BYTE reserved05 ;
WORD secondary_status ;
BYTE PCI_bus ;
BYTE CardBus_bus ;
BYTE subordinate_bus ;
BYTE latency_timer ;
DWORD memory_base0 ;
DWORD memory_limit0 ;
DWORD memory_base1 ;
DWORD memory_limit1 ;
WORD IObase_0low ;
WORD IObase_0high ;
WORD IOlimit_0low ;
WORD IOlimit_0high ;
WORD IObase_1low ;
WORD IObase_1high ;
WORD IOlimit_1low ;
WORD IOlimit_1high ;
BYTE interrupt_line ;
BYTE interrupt_pin ;
WORD bridge_control ;
WORD subsystem_vendorID ;
WORD subsystem_deviceID ;
DWORD legacy_baseaddr ;
DWORD cardbus_reserved[14] ;
DWORD vendor_specific[32] ;
} cardbus ;
} ;
} ;
struct subclass_info
{
int subclass_code ;
const char *subclass_name ;
} ;
#endif
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