syslib.c

VxWorks BSP for S3C44B0X

* Set the processor number for the CPU board.  Processor numbers should be
* unique on a single backplane.
*
* NOTE
* By convention, only processor 0 should dual-port its memory.
*
* RETURNS: N/A
*
* SEE ALSO: sysProcNumGet()
*/

void sysProcNumSet
    (
    int procNum        /* processor number */
    )
    {
    sysProcNum = procNum;
    }

#ifdef INCLUDE_FLASH

/* default procedures assume static ram with no special r/w routines */
#ifndef NV_RAM_WR_ENBL
#   define NV_RAM_WR_ENBL    /* no write enable procedure */
#endif /*NV_RAM_WR_ENBL*/

#ifndef NV_RAM_WR_DSBL
#   define NV_RAM_WR_DSBL    /* no write disable procedure */
#endif /*NV_RAM_WR_DSBL*/

#ifndef NV_RAM_READ
#   define NV_RAM_READ(x) \
    (*(UCHAR *)((int)NV_RAM_ADRS + ((x) * NV_RAM_INTRVL)))
#endif /*NV_RAM_READ*/

#ifndef NV_RAM_WRITE
#   define NV_RAM_WRITE(x,y) \
    (*(UCHAR *)((int)NV_RAM_ADRS + ((x) * NV_RAM_INTRVL)) = (y))
#endif /*NV_RAM_WRITE*/
    
/******************************************************************************
*
* sysNvRamGet - get the contents of non-volatile RAM
*
* This routine copies the contents of non-volatile memory into a specified
* string.  The string is terminated with an EOS.
*
* RETURNS: OK, or ERROR if access is outside the non-volatile RAM range.
*
* SEE ALSO: sysNvRamSet()
*/

STATUS sysNvRamGet
    (
    char *string,    /* where to copy non-volatile RAM    */
    int   strLen,      /* maximum number of bytes to copy   */
    int   offset       /* byte offset into non-volatile RAM */
    )

    {
    STATUS retVal;

    offset += NV_BOOT_OFFSET;   /* boot line begins at <offset> = 0 */

    if ((offset < 0)
     || (strLen < 0)
     || ((offset + strLen) > NV_RAM_SIZE))
        return (ERROR);

    retVal = sysFlashGet (string, strLen, offset);
    string [strLen] = EOS;

    return (OK);
    }

/******************************************************************************
*
* sysNvRamSet - write to non-volatile RAM
*
* This routine copies a specified string into non-volatile RAM.
*
* RETURNS: OK, or ERROR if access is outside the non-volatile RAM range.
*
* SEE ALSO: sysNvRamGet()
*/

STATUS sysNvRamSet
    (
    char *string,     /* string to be copied into non-volatile RAM */
    int strLen,       /* maximum number of bytes to copy           */
    int offset        /* byte offset into non-volatile RAM         */
    )

    {
    offset += NV_BOOT_OFFSET;   /* boot line begins at <offset> = 0 */

    if ((offset < 0)
     || (strLen < 0)
     || ((offset + strLen) > NV_RAM_SIZE))
        return ERROR;

    NV_RAM_WR_ENBL;

    return (sysFlashSet (string, strLen, offset));

    }

/******************************************************************************
*
* sysFlashBoardDelay - create a delay
*
* This routine is used by flashMem.c to produce specified delays. It
* appears that the Flash driver cannot use taskDelay() at certain
* points.
*
* RETURNS: N/A
*/

void sysFlashBoardDelay (void)
    {
    return;
    }
#endif /* INCLUDE_FLASH */


#ifdef INCLUDE_CACHE_SUPPORT

/******************************************************************************
*
* s3c44b0xCacheLibInit - initialize ARM cache library function pointers
*
* This routine initializes the cache library for SNG32C processor.  It
* initializes the function pointers and configures the caches to the
* specified cache modes.  Modes should be set before caching is
* enabled.  If two complementary flags are set (enable/disable), no
* action is taken for any of the input flags.
*
* INTERNAL
* This routine is called (from cacheLibInit()), before sysHwInit has
* been called, and before BSS has been cleared.
*
* RETURNS: OK always
*
*/

STATUS s3c44b0xCacheLibInit
    (
    CACHE_MODE    instMode,    /* instruction cache mode */
    CACHE_MODE    dataMode    /* data cache mode */
    )
    {

#if ((ARMCACHE == ARMCACHE_KS32C))
    cacheLib.enableRtn               = (FUNCPTR) s3c44b0xCacheEnable;
    cacheLib.disableRtn              = (FUNCPTR) s3c44b0xCacheDisable;
    cacheLib.flushRtn                = (FUNCPTR) s3c44b0xCacheFlush;
    cacheLib.invalidateRtn           = (FUNCPTR) NULL;
    cacheLib.clearRtn                = (FUNCPTR) NULL;
    cacheLib.textUpdateRtn           = (FUNCPTR) NULL;
    cacheLib.pipeFlushRtn            = (FUNCPTR) NULL;
    cacheLib.dmaMallocRtn            = (FUNCPTR) s3c44b0xCacheDmaMalloc;
    cacheLib.dmaFreeRtn              = (FUNCPTR) s3c44b0xCacheDmaFree;
    s3c44b0xCacheFuncs.virtToPhysRtn = (FUNCPTR) s3c44b0xVirtToPhysRtn;
    s3c44b0xCacheFuncs.physToVirtRtn = (FUNCPTR) s3c44b0xPhysToVirtRtn;

    if (
    (instMode & CACHE_WRITEALLOCATE)    ||
    (dataMode & CACHE_WRITEALLOCATE)    ||
    (instMode & CACHE_NO_WRITEALLOCATE)    ||
    (dataMode & CACHE_NO_WRITEALLOCATE)    ||
    (instMode & CACHE_SNOOP_ENABLE)        ||
    (dataMode & CACHE_SNOOP_ENABLE)        ||
    (instMode & CACHE_SNOOP_DISABLE)    ||
    (dataMode & CACHE_SNOOP_DISABLE)    ||
    (instMode & CACHE_BURST_ENABLE)        ||
    (dataMode & CACHE_BURST_ENABLE)        ||
    (instMode & CACHE_BURST_DISABLE)    ||
    (dataMode & CACHE_BURST_DISABLE))
        return ERROR;

    /* This has combined Instruction and Data caches */
    if (instMode != dataMode)
        return ERROR;

#else
#error ARMCACHE type not supported here
#endif


    return OK;
    }

/******************************************************************************
*
* s3c44b0xCacheDmaMalloc - allocate a cache-safe buffer
*
* This routine attempts to return a pointer to a section of memory
* that will not experience cache coherency problems.  This routine
* is only called when MMU support is available for cache control.
*
* RETURNS: A pointer to a cache-safe buffer, or NULL.
*
* SEE ALSO: s3c44b0xCacheDmaFree(), cacheDmaMalloc()
*
* NOMANUAL
*/

void * s3c44b0xCacheDmaMalloc
    (
    size_t    bytes    /* size of cache-safe buffer */
    )
    {
    void   *ptr;
    UINT32  foo;

    ptr = malloc (bytes);
    foo = (UINT32)ptr;
    foo |= NON_CACHE_REGION;
    ptr = (void *)foo;

    return (ptr);

    } /* cacheArchDmaMalloc() */

/******************************************************************************
*
* s3c44b0xCacheDmaFree - free the buffer acquired by cacheArchDmaMalloc()
*
* This routine returns to the free memory pool a block of memory previously
* allocated with cacheArchDmaMalloc().  The buffer is marked cacheable.
*
* RETURNS: OK, or ERROR if cacheArchDmaMalloc() cannot be undone.
*
* SEE ALSO: s3c44b0xCacheDmaMalloc(), cacheDmaFree()
*
* NOMANUAL
*/

STATUS s3c44b0xCacheDmaFree
    (
    void *    pBuf        /* ptr returned by cacheArchDmaMalloc() */
    )
    {

    UINT32 foo;

    foo = (UINT32) pBuf;
    foo &= ~NON_CACHE_REGION;
    pBuf = (void *)foo;
	
    free (pBuf);    /* free buffer after modified */

    return OK;

    } /* cacheArchDmaFree() */

/******************************************************************************
*
* s3c44b0xCacheEnable - enable cache
*
* This routine enables cache
*
* RETURNS: void
*
* SEE ALSO: s3c44b0xCacheDisable(), s3c44b0xCacheFlush()
*
* NOMANUAL
*/

void s3c44b0xCacheEnable
    ( 
    void
    )
    {

    UINT32    result;

    /* Clear cache-related bits */
    S3C44B0X_CTRL_REG_READ (S3C44B0X_SYSCFG, result);
/*    S3C44B0X_CTRL_REG_WRITE (S3C44B0X_SYSCFG, (result & 0xffffffC0));*/

    S3C44B0X_CTRL_REG_WRITE (S3C44B0X_SYSCFG, (result & (~S3C44B0X_CACHE_MODE)));
    S3C44B0X_CTRL_REG_READ (S3C44B0X_SYSCFG, result);
	/*  : added */
    S3C44B0X_CTRL_REG_WRITE (S3C44B0X_NCACHBE0, 0xC0000000);

#if (S3C44B0X_CACHE_SIZE == S3C44B0X_CACHE_4K)
    result &= ~S3C44B0X_CACHE_MODE;        /* For 4K Cache */
    /*S3C44B0X_CTRL_REG_WRITE (S3C44B0X_SYSCFG, (result | S3C44B0X_WRITE_BUFF));*/
    s3c44b0xCacheFlush();
	/*  : added */
	S3C44B0X_CTRL_REG_WRITE (S3C44B0X_SYSCFG, (result | S3C44B0X_WRITE_BUFF | S3C44B0X_CACHE_4K));

/*    S3C44B0X_CTRL_REG_READ (S3C44B0X_SYSCFG, result);
    S3C44B0X_CTRL_REG_WRITE (S3C44B0X_SYSCFG, (result | S3C44B0X_CACHE_ENABLE));*/
#endif /* (S3C44B0X_CACHE_SIZE == S3C44B0X_CACHE_4K) */

#if (S3C44B0X_CACHE_SIZE == S3C44B0X_CACHE_8K)	
    result &= ~S3C44B0X_CACHE_MODE;        /* Clear mode bits */
    /*S3C44B0X_CTRL_REG_WRITE (S3C44B0X_SYSCFG,
                            (result | S3C44B0X_WRITE_BUFF | S3C44B0X_CACHE_8K));*/
    s3c44b0xCacheFlush();
	/*  : added */	
	S3C44B0X_CTRL_REG_WRITE (S3C44B0X_SYSCFG, (result | S3C44B0X_WRITE_BUFF | S3C44B0X_CACHE_8K));

/*    S3C44B0X_CTRL_REG_READ (S3C44B0X_SYSCFG, result);
    S3C44B0X_CTRL_REG_WRITE(S3C44B0X_SYSCFG, (result | S3C44B0X_CACHE_ENABLE));*/
#endif /* (S3C44B0X_CACHE_SIZE == S3C44B0X_CACHE_8K) */
    }


/******************************************************************************
*
* s3c44b0xCacheDisable - disable cache
*
* This routine disables cache
*
* RETURNS: void
*
* SEE ALSO: s3c44b0xCacheEnable(), s3c44b0xCacheFlush()
*
* NOMANUAL
*/

void s3c44b0xCacheDisable
    (
    void
    )
    {
    UINT32 result;

    S3C44B0X_CTRL_REG_READ(S3C44B0X_SYSCFG, result);
    S3C44B0X_CTRL_REG_WRITE(S3C44B0X_SYSCFG,
                           (result & ~(S3C44B0X_CACHE_MODE)));

    }

/******************************************************************************
*
* s3c44b0xCacheFlush - flush the cache
*
* This routine flushes the cache
*
* RETURNS: void
*
* SEE ALSO: s3c44b0xCacheEnable(), s3c44b0xCacheDisable()
*
* NOMANUAL
*/

void s3c44b0xCacheFlush(void)
    {
    int i, num;
    UINT32 *tagram;
	UINT32 addr;

	addr = S3C44B0X_TAGRAM_BEG;
	num = (S3C44B0X_TAGRAM_END - S3C44B0X_TAGRAM_BEG)/16;
    s3c44b0xCacheDisable();
    for(i=0; i < num; i++)
    {
        tagram = (UINT32 *)addr;
        *tagram = 0x00000000; 
        addr += 16;
    }
	S3C44B0X_CTRL_REG_WRITE (S3C44B0X_SYSCFG, (S3C44B0X_WRITE_BUFF | S3C44B0X_CACHE_8K));
    }

/******************************************************************************
*
* s3c44b0xPhysToVirtRtn - force memory to cacheable region
*
* This routine clears the "non-cache" bit on an address to force it to use
* the cacheable region of memory
*
* RETURNS: void
*
* SEE ALSO: s3c44b0xCacheEnable(), s3c44b0xCacheDisable()
*
* NOMANUAL
*/

void * s3c44b0xPhysToVirtRtn 
    (
    void *adrs
    )

    {
    UINT32 foo;

    foo = (UINT32)adrs;
    foo &= ~NON_CACHE_REGION;
    adrs = (void *) foo;
    return adrs;
    }

/******************************************************************************
*
* s3c44b0xVirtToPhysRtn - force memory to non-cacheable region
*
* This routine sets the "non-cache" bit on an address to force it to use
* the non-cacheable region of memory
*
* RETURNS: void
*
* SEE ALSO: s3c44b0xCacheEnable(), s3c44b0xCacheDisable()
*
* NOMANUAL
*/

void * s3c44b0xVirtToPhysRtn 
    (
    void *adrs
    )
    
    {
    UINT32 foo;

    foo = (UINT32)adrs;
    foo |= NON_CACHE_REGION;
    adrs = (void *) foo;
    return adrs;
    }

#endif    /* INCLUDE_CACHE_SUPPORT */

#ifdef DEBUG
/******************************************************************************
*
* sysDebug - print message using polled serial driver
*
* Use the polled driver to print debug messages.  Useful before the full
* hardware initialization is complete (but only after sysHwInit).
*
* RETURNS: N/A.
*
* NOMANUAL
*/

void sysDebug
    (
    char *str
    )
    {
    int msgSize;
    int msgIx;
    LOCAL SIO_CHAN * pSioChan;        /* serial I/O channel */
    LOCAL BOOL beenHere = FALSE;

    msgSize = strlen (str);

    if (!beenHere)
        {
        sysSerialHwInit ();

        pSioChan = sysSerialChanGet (0);

        sioIoctl (pSioChan, SIO_BAUD_SET, (void *)CONSOLE_BAUD_RATE);

        sioIoctl (pSioChan, SIO_MODE_SET, (void *) SIO_MODE_POLL);

        beenHere = TRUE;
	}

    for (msgIx = 0; msgIx < msgSize; msgIx++)
        {
        while (sioPollOutput (pSioChan, str[msgIx]) == EAGAIN)
            /* do nothing */;
        }
    }
#endif /* DEBUG */