📄 s3c44b0x.h
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/* s3c44b0x.h - header for Samsung S3C44B0X with ARM7 core */#include "copyright_wrs.h"/*modification history--------------------*/#ifndef __INCs3c44b0x#define __INCs3c44b0x#ifdef __cplusplusextern "C" {#endif/************************************************************************** s3c44b0x SPECIAL REGISTERS *//* System */#define S3C44B0X_SYSCFG (0x1c00000)/* Cache */#define S3C44B0X_NCACHBE0 (0x1c00004)#define S3C44B0X_NCACHBE1 (0x1c00008)/* Bus control */#define S3C44B0X_SBUSCON (0x1c40000) /* Memory control */#define S3C44B0X_BWSCON (0x1c80000)#define S3C44B0X_BANKCON0 (0x1c80004)#define S3C44B0X_BANKCON1 (0x1c80008)#define S3C44B0X_BANKCON2 (0x1c8000c)#define S3C44B0X_BANKCON3 (0x1c80010)#define S3C44B0X_BANKCON4 (0x1c80014)#define S3C44B0X_BANKCON5 (0x1c80018)#define S3C44B0X_BANKCON6 (0x1c8001c)#define S3C44B0X_BANKCON7 (0x1c80020)#define S3C44B0X_REFRESH (0x1c80024)#define S3C44B0X_BANKSIZE (0x1c80028)#define S3C44B0X_MRSRB6 (0x1c8002c)#define S3C44B0X_MRSRB7 (0x1c80030)/* UART */#define S3C44B0X_ULCON0 (0x1d00000)#define S3C44B0X_ULCON1 (0x1d04000)#define S3C44B0X_UCON0 (0x1d00004)#define S3C44B0X_UCON1 (0x1d04004)#define S3C44B0X_UFCON0 (0x1d00008)#define S3C44B0X_UFCON1 (0x1d04008)#define S3C44B0X_UMCON0 (0x1d0000c)#define S3C44B0X_UMCON1 (0x1d0400c)#define S3C44B0X_UTRSTAT0 (0x1d00010)#define S3C44B0X_UTRSTAT1 (0x1d04010)#define S3C44B0X_UERSTAT0 (0x1d00014)#define S3C44B0X_UERSTAT1 (0x1d04014)#define S3C44B0X_UFSTAT0 (0x1d00018)#define S3C44B0X_UFSTAT1 (0x1d04018)#define S3C44B0X_UMSTAT0 (0x1d0001c)#define S3C44B0X_UMSTAT1 (0x1d0401c)#define S3C44B0X_UBRDIV0 (0x1d00028)#define S3C44B0X_UBRDIV1 (0x1d04028)#define S3C44B0X_UTXH0 (0x1d00020)#define S3C44B0X_UTXH1 (0x1d04020)#define S3C44B0X_URXH0 (0x1d00024)#define S3C44B0X_URXH1 (0x1d04024)/* SIO */#define S3C44B0X_SIOCON (0x1d14000)#define S3C44B0X_SIODAT (0x1d14004)#define S3C44B0X_SBRDR (0x1d14008)#define S3C44B0X_IVTCNT (0x1d1400c)#define S3C44B0X_DCNTZ (0x1d14010)/* IIS */#define S3C44B0X_IISCON (0x1d18000)#define S3C44B0X_IISMOD (0x1d18004)#define S3C44B0X_IISPSR (0x1d18008)#define S3C44B0X_IISFCON (0x1d1800c)#define S3C44B0X_IISFIF (0x1d18010)/* I/O PORT */#define S3C44B0X_PCONA (0x1d20000)#define S3C44B0X_PDATA (0x1d20004)#define S3C44B0X_PCONB (0x1d20008)#define S3C44B0X_PDATB (0x1d2000c)#define S3C44B0X_PCONC (0x1d20010)#define S3C44B0X_PDATC (0x1d20014)#define S3C44B0X_PUPC (0x1d20018)#define S3C44B0X_PCOND (0x1d2001c)#define S3C44B0X_PDATD (0x1d20020)#define S3C44B0X_PUPD (0x1d20024)#define S3C44B0X_PCONE (0x1d20028)#define S3C44B0X_PDATE (0x1d2002c)#define S3C44B0X_PUPE (0x1d20030)#define S3C44B0X_PCONF (0x1d20034)#define S3C44B0X_PDATF (0x1d20038)#define S3C44B0X_PUPF (0x1d2003c)#define S3C44B0X_PCONG (0x1d20040)#define S3C44B0X_PDATG (0x1d20044)#define S3C44B0X_PUPG (0x1d20048)#define S3C44B0X_SPUCR (0x1d2004c)#define S3C44B0X_EXTINT (0x1d20050)#define S3C44B0X_EXTINTPND (0x1d20054)/* WATCHDOG */#define S3C44B0X_WTCON (0x1d30000)#define S3C44B0X_WTDAT (0x1d30004)#define S3C44B0X_WTCNT (0x1d30008)/* ADC */#define S3C44B0X_ADCCON (0x1d40000)#define S3C44B0X_ADCPSR (0x1d40004)#define S3C44B0X_ADCDAT (0x1d40008)/* Timer */#define S3C44B0X_TCFG0 (0x1d50000)#define S3C44B0X_TCFG1 (0x1d50004)#define S3C44B0X_TCON (0x1d50008)#define S3C44B0X_TCNTB0 (0x1d5000c)#define S3C44B0X_TCMPB0 (0x1d50010)#define S3C44B0X_TCNTO0 (0x1d50014)#define S3C44B0X_TCNTB1 (0x1d50018)#define S3C44B0X_TCMPB1 (0x1d5001c)#define S3C44B0X_TCNTO1 (0x1d50020)#define S3C44B0X_TCNTB2 (0x1d50024)#define S3C44B0X_TCMPB2 (0x1d50028)#define S3C44B0X_TCNTO2 (0x1d5002c)#define S3C44B0X_TCNTB3 (0x1d50030)#define S3C44B0X_TCMPB3 (0x1d50034)#define S3C44B0X_TCNTO3 (0x1d50038)#define S3C44B0X_TCNTB4 (0x1d5003c)#define S3C44B0X_TCMPB4 (0x1d50040)#define S3C44B0X_TCNTO4 (0x1d50044)#define S3C44B0X_TCNTB5 (0x1d50048)#define S3C44B0X_TCNTO5 (0x1d5004c)/* IIC */#define S3C44B0X_IICCON (0x1d60000)#define S3C44B0X_IICSTAT (0x1d60004)#define S3C44B0X_IICADD (0x1d60008)#define S3C44B0X_IICDS (0x1d6000c)/* RTC */#define S3C44B0X_RTCCON (0x1d70040)#define S3C44B0X_RTCALM (0x1d70050)#define S3C44B0X_ALMSEC (0x1d70054)#define S3C44B0X_ALMMIN (0x1d70058)#define S3C44B0X_ALMHOUR (0x1d7005c)#define S3C44B0X_ALMDAY (0x1d70060)#define S3C44B0X_ALMMON (0x1d70064)#define S3C44B0X_ALMYEAR (0x1d70068)#define S3C44B0X_RTCRST (0x1d7006c)#define S3C44B0X_BCDSEC (0x1d70070)#define S3C44B0X_BCDMIN (0x1d70074)#define S3C44B0X_BCDHOUR (0x1d70078)#define S3C44B0X_BCDDAY (0x1d7007c)#define S3C44B0X_BCDDATE (0x1d70080)#define S3C44B0X_BCDMON (0x1d70084)#define S3C44B0X_BCDYEAR (0x1d70088)#define S3C44B0X_TICINT (0x1d7008c)/* Clock & Power management */#define S3C44B0X_PLLCON (0x1d80000)#define S3C44B0X_CLKCON (0x1d80004)#define S3C44B0X_CLKSLOW (0x1d80008)#define S3C44B0X_LOCKTIME (0x1d8000c)/* INTERRUPT */#define S3C44B0X_INTCON (0x1e00000)#define S3C44B0X_INTPND (0x1e00004)#define S3C44B0X_INTMOD (0x1e00008)#define S3C44B0X_INTMSK (0x1e0000c)#define S3C44B0X_I_PSLV (0x1e00010)#define S3C44B0X_I_PMST (0x1e00014)#define S3C44B0X_I_CSLV (0x1e00018)#define S3C44B0X_I_CMST (0x1e0001c)#define S3C44B0X_I_ISPR (0x1e00020)#define S3C44B0X_I_ISPC (0x1e00024)#define S3C44B0X_F_ISPR (0x1e00038)#define S3C44B0X_F_ISPC (0x1e0003c)/* LCD */#define S3C44B0X_LCDCON1 (0x1f00000)#define S3C44B0X_LCDCON2 (0x1f00004)#define S3C44B0X_LCDCON3 (0x1f00040)#define S3C44B0X_LCDSADDR1 (0x1f00008)#define S3C44B0X_LCDSADDR2 (0x1f0000c)#define S3C44B0X_LCDSADDR3 (0x1f00010)#define S3C44B0X_REDLUT (0x1f00014)#define S3C44B0X_GREENLUT (0x1f00018)#define S3C44B0X_BLUELUT (0x1f0001c)#define S3C44B0X_DP1_2 (0x1f00020)#define S3C44B0X_DP4_7 (0x1f00024)#define S3C44B0X_DP3_5 (0x1f00028)#define S3C44B0X_DP2_3 (0x1f0002c)#define S3C44B0X_DP5_7 (0x1f00030)#define S3C44B0X_DP3_4 (0x1f00034)#define S3C44B0X_DP4_5 (0x1f00038)#define S3C44B0X_DP6_7 (0x1f0003c)#define S3C44B0X_DITHMODE (0x1f00044)/* ZDMA0 */#define S3C44B0X_ZDCON0 (0x1e80000)#define S3C44B0X_ZDISRC0 (0x1e80004)#define S3C44B0X_ZDIDES0 (0x1e80008)#define S3C44B0X_ZDICNT0 (0x1e8000c)#define S3C44B0X_ZDCSRC0 (0x1e80010)#define S3C44B0X_ZDCDES0 (0x1e80014)#define S3C44B0X_ZDCCNT0 (0x1e80018)/* ZDMA1 */#define S3C44B0X_ZDCON1 (0x1e80020)#define S3C44B0X_ZDISRC1 (0x1e80024)#define S3C44B0X_ZDIDES1 (0x1e80028)#define S3C44B0X_ZDICNT1 (0x1e8002c)#define S3C44B0X_ZDCSRC1 (0x1e80030)#define S3C44B0X_ZDCDES1 (0x1e80034)#define S3C44B0X_ZDCCNT1 (0x1e80038)/* BDMA0 */#define S3C44B0X_BDCON0 (0x1f80000)#define S3C44B0X_BDISRC0 (0x1f80004)#define S3C44B0X_BDIDES0 (0x1f80008)#define S3C44B0X_BDICNT0 (0x1f8000c)#define S3C44B0X_BDCSRC0 (0x1f80010)#define S3C44B0X_BDCDES0 (0x1f80014)#define S3C44B0X_BDCCNT0 (0x1f80018)/* BDMA1 */#define S3C44B0X_BDCON1 (0x1f80020)#define S3C44B0X_BDISRC1 (0x1f80024)#define S3C44B0X_BDIDES1 (0x1f80028)#define S3C44B0X_BDICNT1 (0x1f8002c)#define S3C44B0X_BDCSRC1 (0x1f80030)#define S3C44B0X_BDCDES1 (0x1f80034)#define S3C44B0X_BDCCNT1 (0x1f80038)/* read. write register */#define S3C44B0X_REG_READ32(x,result) ((result) = *(volatile unsigned int *)(x))#define S3C44B0X_REG_WRITE32(x,data) (*((volatile unsigned int *)(x)) = (data))/* */#define S3C44B0X_INT_DISABLE (0x3ffffff)#define S3C44B0X_INTNUMLEVELS (26)#define S3C44B0X_INTMASK_VAL (0x3ffffff)#ifdef __cplusplus}#endif#endif /* __INCs3c44b0x */⌨️ 快捷键说明
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