s3c44b0xsio.h

VxWorks BSP for S3C44B0X

/* s3c44b0xSio.h - header file for Samsung KS32C serial driver */

/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01a,12apr01,m_h  created from snds100 template.
*/

#ifndef __INCs3c44b0xSioh
#define __INCs3c44b0xSioh

#ifdef __cplusplus
extern "C" {
#endif

#include "sioLib.h"
#include "s3c44b0x.h"
#include "wrSbcArm7.h"

#define SERIAL_A_BASE_ADR       (0x01D00000)/* UART A base address */
#define SERIAL_B_BASE_ADR       (0x01D04000)/* UART B base address */

/* Register offsets from Base Address*/

#define S3C44B0X_ULCON         0x0000        /*UART Line Control Registers*/
#define S3C44B0X_UCON          0x0004        /*UART Control Register */
#define S3C44B0X_UFCON         0x0008
#define S3C44B0X_UTRSTAT       0x0010        /*UART Status Register */
#define S3C44B0X_UFSTAT        0x0018				 /*UART FIFO status */
#define S3C44B0X_UMSTAT        0x001C
#define S3C44B0X_UTXBUF        0x0020        /*UART Transmit Buffer Register*/
#define S3C44B0X_URXBUF        0x0024        /*UART Receive Buffer Register*/
#define S3C44B0X_UBRDIV        0x0028        /*UART Baud Rate Divisor Register*/

#define S3C44B0X_UCON_VAL   ((0<<9)|(1<<8)|(1<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0))
#define S3C44B0X_UFCON_VAL  ((0<<6)|(0<<4)|(0<<2)|(0<<0))

/* Bit definitions within ULCON0/1 Line Control Register*/

#define PARITY_NONE     (0<<3)          /* Set No Parity*/
#define PARITY_ODD      (4<<3)          /* Set Odd Parity*/
#define PARITY_EVEN     (5<<3)          /* Set Even Parity*/
#define ONE_STOP        (0<<2)          /* One Stop Bit*/
#define WORD_LEN        (3<<0)          /* Set Word Length 8*/

/* Bit definitions within UCON0/1 Control Register*/
#define UCON_RX_MODE     (1<<0)          /* Receive Mode -Interrupt*/
#define UCON_TX_MODE     (1<<2)          /* Transmit Mode-Interrupt*/
#define UCON_BREAK       (1<<4)          /* Set Break*/

#define UCON_RX          0x01            /* Receive Mode -Interrupt*/
#define UCON_TX          0x04            /* Transmit Mode-Interrupt*/
#define UCON_TX_DIS      0x00            /* Transmit Interrupt -Disable*/
#define UCON_RX_TX_RESET 0xff0            /* Rx and Tx Reset */

#define UCON_TX_LEVEL	 0x200	  /* level interrupt */
#define UCON_RX_PULSE	 0x000	    /* pulse interrupt */

/* Bit definitions within USTAT0/1 Status Register*/

#define USTAT_TX_EMPTY  0x04            /* Transmitter Ready for another char */
#define USTAT_RX_READY  0x01            /* Receive Data Buffer*/
#define UTRSTAT_TX_READY  0x04

/* UART Baud Rate Divisor Time Constant Value */
#define COUNT_BSP(bsp)       ((int)(S3C44B0X_CPU_SPEED/16.0/bsp + 0.5) -1)

#define S3C44B0X_CNT0_1200    (COUNT_BSP(1200))    /* Baud_Rate 1200*/
#define S3C44B0X_CNT0_2400    (COUNT_BSP(2400))    /* Baud_Rate 2400*/
#define S3C44B0X_CNT0_4800    (COUNT_BSP(4800))    /* Baud_Rate 4800*/
#define S3C44B0X_CNT0_9600    (COUNT_BSP(9600))    /* Baud_Rate 9600*/
#define S3C44B0X_CNT0_19200   (COUNT_BSP(19200))    /* Baud_Rate 19200*/
#define S3C44B0X_CNT0_38400   (COUNT_BSP(38400))    /* Baud_Rate 38400*/
#define S3C44B0X_CNT0_57600   (COUNT_BSP(57600))    /* Baud_Rate 57600*/
#define S3C44B0X_CNT0_115200  (COUNT_BSP(115200))    /* Baud_Rate 115200*/

#define S3C44B0X_CNT1_VAL         0x00    /* Baud Rate Divisor Value*/

/* device and channel structures */

typedef struct
    {
    /* must be first */
    SIO_CHAN        sio;        /* standard SIO_CHAN element */

    /* callbacks */
    STATUS            (*getTxChar) ();
    STATUS            (*putRcvChar) ();
    void *            getTxArg;
    void *            putRcvArg;

    /* register addresses */
    UINT32 *          regs;        /*UART Registers*/

    /*  interrupts */
    UINT8             intLevelRx;     /* recv interrupt Level for this device*/
    UINT8             intLevelTx;     /* transmit interrupt Level for this device*/

    /* misc */
    UINT32            regDelta;       /* register address spacing */
    uint_t            options;        /* Hardware options */
    int               mode;           /* current mode (interrupt or poll) */
    int               baudRate;       /* input clock frequency */

    } S3C44B0X_CHAN;

/* function prototypes */

#if defined(__STDC__)

extern void    s3c44b0xDevInit  (S3C44B0X_CHAN *pChan); 
extern void    s3c44b0xDevInit2 (S3C44B0X_CHAN *pChan); 
extern void    s3c44b0xIntRcv   (S3C44B0X_CHAN *pChan);
extern void    s3c44b0xIntTx    (S3C44B0X_CHAN *pChan);

#else   /* __STDC__ */

extern void    s3c44b0xDevInit  ();
extern void    s3c44b0xDevInit2 ();
extern void    s3c44b0xIntRcv   ();
extern void    s3c44b0xIntTx    ();

#endif  /* __STDC__ */

#ifdef __cplusplus
}
#endif

#endif  /* __INCs3c44b0xSioh */