rominit.s

VxWorks BSP for S3C44B0X

/* romInit.s - Samsung s3c44b0x ROM initialization module */

/* Copyright elf. */

/*
modification history
--------------------
*/

/*
DESCRIPTION
*/

#define    _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "arch/arm/arm.h"
#include "arch/arm/mmuArmLib.h"
#include "config.h"
#include "regs.h"

    .data
    .globl   FUNC(copyright_wind_river)
    .long    FUNC(copyright_wind_river)

/* internals */

    .globl    FUNC(romInit)    /* start of system code */
    .globl    FUNC(sdata)      /* start of data */
    .globl    _sdata

/* externals */

    .globl    FUNC(romStart)    /* system initialization routine */
    .globl    FUNC(sysModel)

_sdata:
FUNC_LABEL(sdata)
    .asciz    "start of data"
    .balign    4

    .text
    .balign 4

/*******************************************************************************
* romInit - entry point for VxWorks in ROM
*
* romInit
*     (
*     int startType    /@ only used by 2nd entry point @/
*     )

* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/

_ARM_FUNCTION(romInit)
_romInit:
    B    cold
    B    .
    B    .
    B    .
    B    .
    B    .
    B    Irq
    B    .

/* IRQ */
Irq:
    SUB   sp,  sp, #4
    STMFD sp!, {r1}
    LDR   r1,  L_$vec_Irq
    LDR   r1,  [r1]
    STR   r1,  [sp, #4]
    LDMFD sp!, {r1, pc}

cold:
    MOV    r0, #BOOT_COLD    /* fall through to warm boot entry */
warm:
    B    start

    /* copyright notice appears at beginning of ROM (in TEXT segment) */

    .ascii   "Copyright 1984-2001 Wind River Systems, Inc."
    .balign 4

start:
    MOV    r13,  r0    /* Save starttype in r13 so that r0 can be used for other purposes */

    /* Disable WDT */
    LDR	   r2, L_$s3c44b0x_WTCON
    MOV    r1, #0
    STR    r1, [r2]

    /* disable interrupts in CPU and switch to SVC32 mode */
    MRS    r1,   cpsr
    BIC    r1,   r1,  #MASK_32MODE
    ORR    r1,   r1,  #MODE_SVC32 | I_BIT | F_BIT
    MSR    cpsr, r1

    /*
     * CPU INTERRUPTS DISABLED
     * disable individual interrupts in the interrupt controller
     */
    LDR    r2, L_$s3c44b0x_INTMSK   /* R2->interrupt controller */
    MVN    r1, #0                   /* &FFFFFFFF */
    STR    r1, [r2]                 /* disable all interrupt sources */

   	/* Set sys clock */
    LDR		r0,   L_$s3c44b0x_LOCKTIME
    LDR		r1,   L_$s3c44b0x_LOCKTIME_VAL
    STR		r1,   [r0]

	LDR		r0,   L_$s3c44b0x_PLLCON
    LDR		r1,   L_$s3c44b0x_PLLCON_VAL
    STR		r1,   [r0]

    LDR   r0,   L_$s3c44b0x_CLKCON
    LDR	  r1,   L_$s3c44b0x_CLKCON_VAL
    STR	  r1,   [r0]

    /*
     * If not BOOT_COLD, bypass memory configuration, memory region
     * switching etc.
     */
    CMP    r0, #BOOT_COLD
    BNE    HiPosn

/* init SDRAM con */
SYNC_DRAM:

    LDR    r0, L_$s3c44b0x_SYSCFG
    LDR    r1, L_$s3c44b0x_SYSCFG_VAL
    STR    r1, [r0]             /* Cache,WB disable */

    LDR    r1, L_$SystemInitDataSDRAM
    LDR    r2, L_$SystemInitDataSDRAM + 0x04
    LDR    r3, L_$SystemInitDataSDRAM + 0x08
    LDR    r4, L_$SystemInitDataSDRAM + 0x0c
    LDR    r5, L_$SystemInitDataSDRAM + 0x10
    LDR    r6, L_$SystemInitDataSDRAM + 0x14
    LDR    r7, L_$SystemInitDataSDRAM + 0x18
    LDR    r8, L_$SystemInitDataSDRAM + 0x1c
    LDR    r9, L_$SystemInitDataSDRAM + 0x20
    LDR    r10,L_$SystemInitDataSDRAM + 0x24
    LDR    r11,L_$SystemInitDataSDRAM + 0x28
    LDR    r12,L_$SystemInitDataSDRAM + 0x2c
    LDR    r0, L_$s3c44b0xExtdbwth         /* Extdbwth Offset : 0x3010 */
    STMIA  r0, {r1-r12}

    /*  : r13存储启动类型,不能使用 */
    LDR    r0, L_$s3c44b0xMrsrb7
    LDR    r1, L_$SystemInitDataSDRAM +0x30
    STR    r1, [r0]

/*=============================================================
 * Copy to DRAM the section of ROM in which we are currently executing.
 * Soon, we will set the base pointer of DRAM to where the base pointer of
 * ROM used to be.  At that point the PC will suddenly be set in RAM and
 * must have legitimate code to execute.
 *=============================================================
 */

    MOV    r0, #RESET_ROM_START         /* Get pointer to ROM data */
    LDR    r1, L_$RomCopySize           /* number of ROM bytes to copy into RAM */
    MOV    r2, #RESET_DRAM_START        /* Copy DRAM area base */

ROM2SDRAM_COPY_LOOP:
    LDR    r3, [r0], #4
    STR    r3, [r2], #4
    SUBS   r1, r1, #4         /* Down Count */
    BNE    ROM2SDRAM_COPY_LOOP
    LDR    PC, L_$HiPosn

HiPosn:
    /*
     * Initialize the stack pointer to just before where the
     * uncompress code, copied from ROM to RAM, will run.
     */
    MOV    r0, r13        /* restore starttype to r0 from r13 */
    LDR    sp, L_$STACK_ADDR
    MOV    fp, #0            /* zero frame pointer */


    /* jump to C entry point in ROM: routine - entry point + ROM base */
#if    (CPU == ARMARCH4_T)
    LDR    r12, L_$rStrtInRom
    ORR    r12, r12, #1        /* force Thumb state */
    BX     r12
#else
    LDR    pc, L_$rStrtInRom
#endif    /* (CPU == ARMARCH4_T) */

/******************************************************************************/

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor preforming substitution
 */
    .balign    4

L_$HiPosn:
    .long    ROM_TEXT_ADRS + HiPosn - FUNC(romInit)

L_$vec_Irq:
    .long    0

L_$s3c44b0x_INTMSK:
    .long    S3C44B0X_INTMSK

L_$s3c44b0x_WTCON:
		.long    S3C44B0X_WTCON

L_$s3c44b0x_LOCKTIME:
		.long  S3C44B0X_LOCKTIME
L_$s3c44b0x_LOCKTIME_VAL:
		.long  0xfff

L_$s3c44b0x_PLLCON:
		.long  S3C44B0X_PLLCON
L_$s3c44b0x_PLLCON_VAL:
		.long  ((56<<12)+(3<<4)+1)

L_$s3c44b0x_CLKCON:
		.long   S3C44B0X_CLKCON
L_$s3c44b0x_CLKCON_VAL:
		.long		0x7ff8

L_$s3c44b0xExtdbwth:
    .long    S3C44B0X_BWSCON	/*  : SNGKS32C_EXTDBWTH->S3C44B0X_BWSCON */

L_$s3c44b0xMrsrb7:               /*  : added */
    .long    S3C44B0X_MRSRB7

L_$s3c44b0x_SYSCFG:
    .long   S3C44B0X_SYSCFG
L_$s3c44b0x_SYSCFG_VAL:
		.long   0

L_$STACK_ADDR:
    .long    STACK_ADRS

L_$SystemInitDataSDRAM:
    .long    rEXTDBWTH    /* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */
    .long    rROMCON0    /* 0x0000000 ~ 0x40000, ROM0,256K,2cycle */
    .long    rROMCON1
    .long    rROMCON2
    .long    rROMCON3
    .long    rROMCON4
    .long    rROMCON5
    .long    rSDRAMCON0    /* 0x1000000 ~ 0x13FFFFF, DRAM0 4M, */
    .long    rSDRAMCON1

    .long    rSREFEXTCON
    .long    rBANKSIZE
    .long    rMRSRB6
    .long    rMRSRB7

L_$rStrtInRom:
    .long    ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)

L_$RomCopySize:
    .long    L_$RomCopySize - FUNC(romInit)