wrsbcarm7.h

VxWorks BSP for S3C44B0X

/* sbcarm7.h - WindRiver SBC ARM7 header file */


/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
*/

/*
This file contains I/O address and related constants for the SBC ARM7 board.
*/

#ifndef    INCsbcarm7h
#define    INCsbcarm7h

#ifdef __cplusplus
extern "C" {
#endif

#include "s3c44b0x.h"

#define TARGET_SBCARM7

/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS  0x00000000    /* fixed */
#define LOCAL_MEM_BUS_ADRS    0x00000000    /* fixed */

#define BUS                   BUS_TYPE_NONE

/*************************************************************************
 *
 * DRAM Memory Bank 0 area MAP for Exception vector table 
 * and Stack, User code area. 
 *
 */
/*  : 0x00000000->0x0c000000 */
#define DRAM_BASE           0x0c000000   /* Final start address of DRAM */
#define DRAM_LIMIT          0x400000
/*  : 0x1000000->0x0c000000 */
#define RESET_DRAM_START    0x0c000000   /* Start of DRAM on power-up */
#define RESET_ROM_START     0x0          /* Start of ROM on power-up */

/* definitions for the s3c44b0x UART */

#define N_S3C44B0X_UART_CHANNELS  2        /* number of s3c44b0x UART chans */
#define N_SIO_CHANNELS            N_S3C44B0X_UART_CHANNELS
#define N_UART_CHANNELS           N_S3C44B0X_UART_CHANNELS
#define UART_REG_ADDR_INTERVAL    1        /* registers 4 bytes apart */

/*************************************************************************
 * SYSTEM CLOCK 
 */
#define S3C44B0X_CPU_SPEED         64000000    /* CPU clocked at 64 MHz. The timer */

/*************************************************************************
 * SYSTEM MEMORY CONTROL REGISTER EQU TABLES 
 */


/* interrupt levels */

#define INT_LVL_ADC        0
#define INT_LVL_RTC        1
#define INT_LVL_UTXD1      2
#define INT_LVL_UTXD0      3
#define INT_LVL_SIO        4
#define INT_LVL_IIC        5
#define INT_LVL_URXD1      6
#define INT_LVL_URXD0      7
#define INT_LVL_TIMER5     8
#define INT_LVL_TIMER4     9
#define INT_LVL_TIMER3     10
#define INT_LVL_TIMER2     11
#define INT_LVL_TIMER1     12
#define INT_LVL_TIMER0     13
#define INT_LVL_UERR0_1    14
#define INT_LVL_WDT        15
#define INT_LVL_BDMA1      16
#define INT_LVL_BDMA0      17
#define INT_LVL_ZDMA1      18
#define INT_LVL_ZDMA0      19
#define INT_LVL_TICK       20
#define INT_LVL_EINT4567   21
#define INT_LVL_EINT3      22
#define INT_LVL_EINT2      23
#define INT_LVL_EINT1      24
#define INT_LVL_EINT0      25

/* interrupt vectors */

#define INT_VEC_ADC     IVEC_TO_INUM(INT_LVL_ADC)
#define INT_VEC_RTC     IVEC_TO_INUM(INT_LVL_RTC)
#define INT_VEC_UTXD1   IVEC_TO_INUM(INT_LVL_UTXD1)
#define INT_VEC_UTXD0   IVEC_TO_INUM(INT_LVL_UTXD0)
#define INT_VEC_SIO     IVEC_TO_INUM(INT_LVL_SIO)
#define INT_VEC_IIC     IVEC_TO_INUM(INT_LVL_IIC)
#define INT_VEC_URXD1   IVEC_TO_INUM(INT_LVL_URXD1)
#define INT_VEC_URXD0   IVEC_TO_INUM(INT_LVL_URXD0)
#define INT_VEC_TIMER5  IVEC_TO_INUM(INT_LVL_TIMER5)
#define INT_VEC_TIMER4  IVEC_TO_INUM(INT_LVL_TIMER4)
#define INT_VEC_TIMER3  IVEC_TO_INUM(INT_LVL_TIMER3)
#define INT_VEC_TIMER2  IVEC_TO_INUM(INT_LVL_TIMER2)
#define INT_VEC_TIMER1  IVEC_TO_INUM(INT_LVL_TIMER1)
#define INT_VEC_TIMER0  IVEC_TO_INUM(INT_LVL_TIMER0)
#define INT_VEC_UERR0_1 IVEC_TO_INUM(INT_LVL_UERR0_1)
#define INT_VEC_WDT     IVEC_TO_INUM(INT_LVL_WDT)
#define INT_VEC_BDMA1   IVEC_TO_INUM(INT_LVL_BDMA1)
#define INT_VEC_BDMA0   IVEC_TO_INUM(INT_LVL_BDMA0)
#define INT_VEC_ZDMA1   IVEC_TO_INUM(INT_LVL_ZDMA1)
#define INT_VEC_ZDMA0   IVEC_TO_INUM(INT_LVL_ZDMA0)
#define INT_VEC_TICK    IVEC_TO_INUM(INT_LVL_TICK)
#define INT_VEC_EINT4567   IVEC_TO_INUM(INT_LVL_EINT4567)
#define INT_VEC_EINT3   IVEC_TO_INUM(INT_LVL_EINT3)
#define INT_VEC_EINT2   IVEC_TO_INUM(INT_LVL_EINT2)
#define INT_VEC_EINT1   IVEC_TO_INUM(INT_LVL_EINT1)
#define INT_VEC_EINT0   IVEC_TO_INUM(INT_LVL_EINT0)

/**********************************************************************************************************
 * Cache Definitions
 *
 */

#define S3C44B0X_CACHE_0K   	 	(0<<1)
#define S3C44B0X_CACHE_4K        (1<<1)
#define S3C44B0X_CACHE_8K        (3<<1)
#define S3C44B0X_WRITE_BUFF      (1<<3)
#define S3C44B0X_CACHE_MODE      0x0E

#define S3C44B0X_CACHE_SIZE		S3C44B0X_CACHE_8K

#define NON_CACHE_REGION    	0		/*TODO*/
/*#define S3C44B0X_TAGRAM          0x11000000*/
#define S3C44B0X_TAGRAM_BEG 0x10002000  /*CACHE TAG RAM起始地址*/
#define S3C44B0X_TAGRAM_END 0x10004800  /*CACHE TAG RAM结束地址*/


/*
 *
 * definitions for the s3c44b0x Timer:
 * two timers clocked from same source and with the same reload overhead
 */

#define SYS_TIMER_INT_LVL           (INT_LVL_TIMER5)
#define AUX_TIMER_INT_LVL           (INT_LVL_TIMER1)

/******************************************************************************************
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * Note that it takes 3 ticks to reload the 16-bit counter and we don't
 * accept values that would mean a zero reload value as we don't know what
 * that will do.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value+3))
 * max frequency = rounddown(clock_rate/(min_counter_value+3))
 * i.e.              SYS_CLK_RATE_MAX (SYS_TIMER_CLK/4)
 * However, we must set maxima that are sustainable on a running
 * system. Experiments suggest that a 16MHz PID board can sustain a
 * maximum clock rate of 10000 to 10500. The values below have been
 * chosen so that there is a reasonable margin and the BSP passes the
 * test suite.
 */

#define SYS_CLK_RATE_MIN      10
#define SYS_CLK_RATE_MAX      1000
#define AUX_CLK_RATE_MIN      2
#define AUX_CLK_RATE_MAX      1000

#define SYS_TIMER_CLK               (S3C44B0X_CPU_SPEED)    /* Frequency of counter/timer */
#define AUX_TIMER_CLK               (S3C44B0X_CPU_SPEED)    /* Frequency of counter/timer */

/*
 * Our MAC address definition.  User can change this value as
 * per requirement.  Note, the least significant byte of the
 * address is changed to the value of the user DIP switch setting.
 * SW4-D0 is the least significant bit of this byte.  Open=0.
 */

#define ETHERNET_MAC_ADRS { 0x00, 0xA0, 0x88, 0x88, 0x88, 0x00 }


/*#define rEXTDBWTH     (DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3)*/
/*  : deleted and added */
#define rEXTDBWTH  		0x11110010

/*  : added++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/*FLASH0*/
#define B0_Tacs         0x0     /*0clk*/
#define B0_Tcos         0x0     /*0clk*/
#define B0_Tacc         0x6     /*10clk*/
#define B0_Tcoh         0x0     /*0clk*/
#define B0_Tah          0x0     /*0clk*/
#define B0_Tacp         0x0     /*0clk*/
#define B0_PMC          0x0     /*normal(1data)*/
#define rROMCON0 ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
/*FLASH1*/
#define rROMCON1		rROMCON0
/*CPLD1 External (CF Card)*/
#define B2_Tacs         0x3     /*4clk*/
#define B2_Tcos         0x3     /*4clk*/
#define B2_Tacc         0x7     /*14clk*/
#define B2_Tcoh         0x3     /*4clk*/
#define B2_Tah          0x3     /*4clk*/
#define B2_Tacp         0x3     /*6clk*/
#define B2_PMC          0x0     /*normal(1data)*/
#define rROMCON2 ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
/*CPLD2 Exernal (Net)*/
#define rROMCON3		rROMCON2
/*CPLD3 USER FREE*/
#define rROMCON4		rROMCON2
/*CPLD4 Internal*/
#define rROMCON5		rROMCON2

/*SDRAM1 Bank 6 parameter*/
/*BDRAMTYPE="DRAM"       ;MT=01(FP DRAM) or 10(EDO DRAM)*/ 
#define B6_MT           0x3     /*SDRAM*/
#define B6_Trcd         0x0     /*2clk*/
#define B6_SCAN         0x1     /*8bit*/
#define rSDRAMCON0 ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
/*SDRAM2 Bank 7 parameter*/
#define rSDRAMCON1		rSDRAMCON0

/*REFRESH parameter*/
#define REFEN           0x1     /*Refresh enable*/
#define TREFMD          0x0     /*CBR(CAS before RAS)/Auto refresh*/
#define Trp             0x2     /*3clk*/
#define Trc             0x1     /*5clk*/
#define Tchr            0x2     /*3clk*/
/*REFCNT = 2048 + 1 - MCLK(MHz) * 15.6*/
#define REFCNT          1050    /*period=15.6us, MCLK=66Mhz*/
#define rSREFEXTCON ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)

#define rBANKSIZE		0x10	/*SCLK power down mode, BANKSIZE 32M/32M*/
#define rMRSRB6			0x20	/*MRSR6 CL=2clk*/
#define rMRSRB7			0x20	/*MRSR7*/

#ifdef __cplusplus
}
#endif

#endif    /* INCsbcarm7h */