xmac_ii.h

u-boot-1.1.2 for cayman 开发板（其他板试过也能用。

 * Xmac/Broadcom/LevelOne/National-specific.
 * All other are general.
 */

/*****  PHY_XMAC_CTRL	16 bit r/w	PHY Control Register *****/
/*****  PHY_BCOM_CTRL	16 bit r/w	PHY Control Register *****/
/*****  PHY_LONE_CTRL	16 bit r/w	PHY Control Register *****/
#define PHY_CT_RESET	(1<<15)	/* Bit 15: (sc)	clear all PHY related regs */
#define PHY_CT_LOOP		(1<<14)	/* Bit 14:	enable Loopback over PHY */
#define PHY_CT_SPS_LSB	(1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
#define PHY_CT_ANE		(1<<12)	/* Bit 12:	Auto-Negotiation Enabled */
#define PHY_CT_PDOWN	(1<<11)	/* Bit 11: (BC,L1) Power Down Mode */
#define PHY_CT_ISOL		(1<<10)	/* Bit 10: (BC,L1) Isolate Mode */
#define PHY_CT_RE_CFG	(1<<9)	/* Bit  9: (sc) Restart Auto-Negotiation */
#define PHY_CT_DUP_MD	(1<<8)	/* Bit  8:	Duplex Mode */
#define PHY_CT_COL_TST	(1<<7)	/* Bit  7: (BC,L1) Collision Test enabled */
#define PHY_CT_SPS_MSB	(1<<6)	/* Bit  6: (BC,L1) Speed select, upper bit */
								/* Bit  5..0:	reserved */

#define PHY_CT_SP1000	PHY_CT_SPS_MSB	/* enable speed of 1000 Mbps */
#define PHY_CT_SP100	PHY_CT_SPS_LSB	/* enable speed of  100 Mbps */
#define PHY_CT_SP10		(0)				/* enable speed of   10 Mbps */


/*****  PHY_XMAC_STAT	16 bit r/w	PHY Status Register *****/
/*****  PHY_BCOM_STAT	16 bit r/w	PHY Status Register *****/
/*****  PHY_MARV_STAT	16 bit r/w	PHY Status Register *****/
/*****  PHY_LONE_STAT	16 bit r/w	PHY Status Register *****/
								/* Bit 15..9:	reserved */
				/*	(BC/L1) 100/10 Mbps cap bits ignored*/
#define PHY_ST_EXT_ST	(1<<8)	/* Bit  8:	Extended Status Present */
								/* Bit  7:	reserved */
#define PHY_ST_PRE_SUP	(1<<6)	/* Bit  6: (BC/L1) preamble suppression */
#define PHY_ST_AN_OVER	(1<<5)	/* Bit  5:	Auto-Negotiation Over */
#define PHY_ST_REM_FLT	(1<<4)	/* Bit  4:	Remote Fault Condition Occured */
#define PHY_ST_AN_CAP	(1<<3)	/* Bit  3:	Auto-Negotiation Capability */
#define PHY_ST_LSYNC	(1<<2)	/* Bit  2:	Link Synchronized */
#define PHY_ST_JAB_DET	(1<<1)	/* Bit  1: (BC/L1) Jabber Detected */
#define PHY_ST_EXT_REG	(1<<0)	/* Bit  0:	Extended Register available */


/*****	PHY_XMAC_ID1		16 bit r/o	PHY ID1 Register */
/*****	PHY_BCOM_ID1		16 bit r/o	PHY ID1 Register */
/*****	PHY_MARV_ID1		16 bit r/o	PHY ID1 Register */
/*****	PHY_LONE_ID1		16 bit r/o	PHY ID1 Register */
#define PHY_I1_OUI_MSK	(0x3f<<10)	/* Bit 15..10:	Organization Unique ID */
#define PHY_I1_MOD_NUM	(0x3f<<4)	/* Bit  9.. 4:	Model Number */
#define PHY_I1_REV_MSK	0x0f		/* Bit  3.. 0:	Revision Number */

/* different Broadcom PHY Ids */
#define PHY_BCOM_ID1_A1		0x6041
#define PHY_BCOM_ID1_B2		0x6043
#define PHY_BCOM_ID1_C0		0x6044
#define PHY_BCOM_ID1_C5		0x6047


/*****  PHY_XMAC_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
/*****  PHY_XMAC_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
#define PHY_AN_NXT_PG	(1<<15)	/* Bit 15:	Request Next Page */
#define PHY_X_AN_ACK	(1<<14)	/* Bit 14: (ro)	Acknowledge Received */
#define PHY_X_AN_RFB	(3<<12)	/* Bit 13..12:	Remote Fault Bits */
								/* Bit 11.. 9:	reserved */
#define PHY_X_AN_PAUSE	(3<<7)	/* Bit  8.. 7:	Pause Bits */
#define PHY_X_AN_HD		(1<<6)	/* Bit  6:	Half Duplex */
#define PHY_X_AN_FD		(1<<5)	/* Bit  5:	Full Duplex */
								/* Bit  4.. 0:	reserved */

/*****  PHY_BCOM_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
/*****  PHY_BCOM_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
								/* Bit 14:	reserved */
#define PHY_B_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
								/* Bit 12:	reserved */
#define PHY_B_AN_ASP	(1<<11)	/* Bit 11:	Asymmetric Pause */
#define PHY_B_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
								/* Bit  9..5:	100/10 BT cap bits ingnored */
#define PHY_B_AN_SEL	0x1f	/* Bit 4..0:	Selector Field, 00001=Ethernet*/

/*****  PHY_LONE_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
/*****  PHY_LONE_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
								/* Bit 14:	reserved */
#define PHY_L_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
								/* Bit 12:	reserved */
#define PHY_L_AN_ASP	(1<<11)	/* Bit 11:	Asymmetric Pause */
#define PHY_L_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
								/* Bit  9..5:	100/10 BT cap bits ingnored */
#define PHY_L_AN_SEL	0x1f	/* Bit 4..0:	Selector Field, 00001=Ethernet*/

/*****  PHY_NAT_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
/*****  PHY_NAT_AUNE_LP		16 bit r/o	Link Partner Ability Reg *****/
/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
								/* Bit 14:	reserved */
#define PHY_N_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
								/* Bit 12:	reserved */
#define PHY_N_AN_100F	(1<<11)	/* Bit 11:	100Base-T2 FD Support */
#define PHY_N_AN_100H	(1<<10)	/* Bit 10:	100Base-T2 HD Support */
								/* Bit  9..5:	100/10 BT cap bits ingnored */
#define PHY_N_AN_SEL	0x1f	/* Bit 4..0:	Selector Field, 00001=Ethernet*/

/* field type definition for PHY_x_AN_SEL */
#define PHY_SEL_TYPE	0x01	/* 00001 = Ethernet */

/*****  PHY_XMAC_AUNE_EXP	16 bit r/o	Auto-Negotiation Expansion Reg *****/
								/* Bit 15..4:	reserved */
#define PHY_AN_LP_NP	(1<<3)	/* Bit  3:	Link Partner can Next Page */
#define PHY_AN_LOC_NP	(1<<2)	/* Bit  2:	Local PHY can Next Page */
#define PHY_AN_RX_PG	(1<<1)	/* Bit  1:	Page Received */
								/* Bit  0:	reserved */

/*****  PHY_BCOM_AUNE_EXP	16 bit r/o	Auto-Negotiation Expansion Reg *****/
								/* Bit 15..5:	reserved */
#define PHY_B_AN_PDF	(1<<4)	/* Bit  4:	Parallel Detection Fault */
/*	PHY_AN_LP_NP		(see XMAC) Bit  3:	Link Partner can Next Page */
/*	PHY_AN_LOC_NP		(see XMAC) Bit  2:	Local PHY can Next Page */
/*	PHY_AN_RX_PG		(see XMAC) Bit  1:	Page Received */
#define PHY_B_AN_LP_CAP	(1<<0)	/* Bit  0:	Link Partner Auto-Neg. Cap. */

/*****  PHY_LONE_AUNE_EXP	16 bit r/o	Auto-Negotiation Expansion Reg *****/
#define PHY_L_AN_BP		(1<<5)	/* Bit  5:	Base Page Indication */
#define PHY_L_AN_PDF	(1<<4)	/* Bit  4:	Parallel Detection Fault */
/*	PHY_AN_LP_NP		(see XMAC) Bit  3:	Link Partner can Next Page */
/*	PHY_AN_LOC_NP		(see XMAC) Bit  2:	Local PHY can Next Page */
/*	PHY_AN_RX_PG		(see XMAC) Bit  1:	Page Received */
#define PHY_B_AN_LP_CAP	(1<<0)	/* Bit  0:	Link Partner Auto-Neg. Cap. */


/*****  PHY_XMAC_NEPG		16 bit r/w	Next Page Register *****/
/*****  PHY_BCOM_NEPG		16 bit r/w	Next Page Register *****/
/*****  PHY_LONE_NEPG		16 bit r/w	Next Page Register *****/
/*****  PHY_XMAC_NEPG_LP	16 bit r/o	Next Page Link Partner *****/
/*****  PHY_BCOM_NEPG_LP	16 bit r/o	Next Page Link Partner *****/
/*****  PHY_LONE_NEPG_LP	16 bit r/o	Next Page Link Partner *****/
#define PHY_NP_MORE		(1<<15)	/* Bit 15:	More, Next Pages to follow */
#define PHY_NP_ACK1		(1<<14)	/* Bit 14: (ro)	Ack 1, for receiving a message*/
#define PHY_NP_MSG_VAL	(1<<13)	/* Bit 13:	Message Page valid */
#define PHY_NP_ACK2		(1<<12)	/* Bit 12:	Ack 2, comply with msg content*/
#define PHY_NP_TOG		(1<<11)	/* Bit 11:	Toggle Bit, ensure sync */
#define PHY_NP_MSG		0x07ff	/* Bit 10..0:	Message from/to Link Partner */

/*
 * XMAC-Specific
 */
/*****  PHY_XMAC_EXT_STAT	16 bit r/w	Extended Status Register *****/
#define PHY_X_EX_FD		(1<<15)	/* Bit 15:	Device Supports Full Duplex */
#define PHY_X_EX_HD		(1<<14)	/* Bit 14:	Device Supports Half Duplex */
								/* Bit 13..0:	reserved */

/*****  PHY_XMAC_RES_ABI	16 bit r/o	PHY Resolved Ability *****/
								/* Bit 15..9:	reserved */
#define PHY_X_RS_PAUSE	(3<<7)	/* Bit  8..7:	selected Pause Mode */
#define PHY_X_RS_HD		(1<<6)	/* Bit  6:	Half Duplex Mode selected */
#define PHY_X_RS_FD		(1<<5)	/* Bit  5:	Full Duplex Mode selected */
#define PHY_X_RS_ABLMIS (1<<4)	/* Bit  4:	duplex or pause cap mismatch */
#define PHY_X_RS_PAUMIS (1<<3)	/* Bit  3:	pause capability missmatch */
								/* Bit  2..0:	reserved */
/*
 * Remote Fault Bits (PHY_X_AN_RFB) encoding
 */
#define X_RFB_OK		(0<<12)	/* Bit 13..12	No errors, Link OK */
#define X_RFB_LF		(1<<12)	/* Bit 13..12	Link Failure */
#define X_RFB_OFF		(2<<12)	/* Bit 13..12	Offline */
#define X_RFB_AN_ERR	(3<<12)	/* Bit 13..12	Auto-Negotiation Error */

/*
 * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding
 */
#define PHY_X_P_NO_PAUSE	(0<<7)	/* Bit  8..7:	no Pause Mode */
#define PHY_X_P_SYM_MD		(1<<7)	/* Bit  8..7:	symmetric Pause Mode */
#define PHY_X_P_ASYM_MD		(2<<7)	/* Bit  8..7:	asymmetric Pause Mode */
#define PHY_X_P_BOTH_MD		(3<<7)	/* Bit  8..7:	both Pause Mode */


/*
 * Broadcom-Specific
 */
/*****  PHY_BCOM_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
#define PHY_B_1000C_TEST	(7<<13)	/* Bit 15..13:	Test Modes */
#define PHY_B_1000C_MSE		(1<<12)	/* Bit 12:	Master/Slave Enable */
#define PHY_B_1000C_MSC		(1<<11)	/* Bit 11:	M/S Configuration */
#define PHY_B_1000C_RD		(1<<10)	/* Bit 10:	Repeater/DTE */
#define PHY_B_1000C_AFD		(1<<9)	/* Bit  9:	Advertise Full Duplex */
#define PHY_B_1000C_AHD		(1<<8)	/* Bit  8:	Advertise Half Duplex */
									/* Bit  7..0:	reserved */

/*****  PHY_BCOM_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
#define PHY_B_1000S_MSF		(1<<15)	/* Bit 15:	Master/Slave Fault */
#define PHY_B_1000S_MSR		(1<<14)	/* Bit 14:	Master/Slave Result */
#define PHY_B_1000S_LRS		(1<<13)	/* Bit 13:	Local Receiver Status */
#define PHY_B_1000S_RRS		(1<<12)	/* Bit 12:	Remote Receiver Status */
#define PHY_B_1000S_LP_FD	(1<<11)	/* Bit 11:	Link Partner can FD */
#define PHY_B_1000S_LP_HD	(1<<10)	/* Bit 10:	Link Partner can HD */
									/* Bit  9..8:	reserved */
#define PHY_B_1000S_IEC		0xff	/* Bit  7..0:	Idle Error Count */

/*****  PHY_BCOM_EXT_STAT	16 bit r/o	Extended Status Register *****/
#define PHY_B_ES_X_FD_CAP	(1<<15)	/* Bit 15:	1000Base-X FD capable */
#define PHY_B_ES_X_HD_CAP	(1<<14)	/* Bit 14:	1000Base-X HD capable */
#define PHY_B_ES_T_FD_CAP	(1<<13)	/* Bit 13:	1000Base-T FD capable */
#define PHY_B_ES_T_HD_CAP	(1<<12)	/* Bit 12:	1000Base-T HD capable */
									/* Bit 11..0:	reserved */

/*****  PHY_BCOM_P_EXT_CTRL	16 bit r/w	PHY Extended Control Reg *****/
#define PHY_B_PEC_MAC_PHY	(1<<15)	/* Bit 15:	10BIT/GMI-Interface */
#define PHY_B_PEC_DIS_CROSS	(1<<14)	/* Bit 14:	Disable MDI Crossover */
#define PHY_B_PEC_TX_DIS	(1<<13)	/* Bit 13:	Tx output Disabled */
#define PHY_B_PEC_INT_DIS	(1<<12)	/* Bit 12:	Interrupts Disabled */
#define PHY_B_PEC_F_INT		(1<<11)	/* Bit 11:	Force Interrupt */
#define PHY_B_PEC_BY_45		(1<<10)	/* Bit 10:	Bypass 4B5B-Decoder */
#define PHY_B_PEC_BY_SCR	(1<<9)	/* Bit  9:	Bypass Scrambler */
#define PHY_B_PEC_BY_MLT3	(1<<8)	/* Bit  8:	Bypass MLT3 Encoder */
#define PHY_B_PEC_BY_RXA	(1<<7)	/* Bit  7:	Bypass Rx Alignm. */
#define PHY_B_PEC_RES_SCR	(1<<6)	/* Bit  6:	Reset Scrambler */
#define PHY_B_PEC_EN_LTR	(1<<5)	/* Bit  5:	Ena LED Traffic Mode */
#define PHY_B_PEC_LED_ON	(1<<4)	/* Bit  4:	Force LED's on */
#define PHY_B_PEC_LED_OFF	(1<<3)	/* Bit  3:	Force LED's off */
#define PHY_B_PEC_EX_IPG	(1<<2)	/* Bit  2:	Extend Tx IPG Mode */
#define PHY_B_PEC_3_LED		(1<<1)	/* Bit  1:	Three Link LED mode */
#define PHY_B_PEC_HIGH_LA	(1<<0)	/* Bit  0:	GMII FIFO Elasticy */

/*****  PHY_BCOM_P_EXT_STAT	16 bit r/o	PHY Extended Status Reg *****/
									/* Bit 15..14:	reserved */
#define PHY_B_PES_CROSS_STAT	(1<<13)	/* Bit 13:	MDI Crossover Status */
#define PHY_B_PES_INT_STAT	(1<<12)	/* Bit 12:	Interrupt Status */
#define PHY_B_PES_RRS		(1<<11)	/* Bit 11:	Remote Receiver Stat. */
#define PHY_B_PES_LRS		(1<<10)	/* Bit 10:	Local Receiver Stat. */
#define PHY_B_PES_LOCKED	(1<<9)	/* Bit  9:	Locked */
#define PHY_B_PES_LS		(1<<8)	/* Bit  8:	Link Status */
#define PHY_B_PES_RF		(1<<7)	/* Bit  7:	Remote Fault */
#define PHY_B_PES_CE_ER		(1<<6)	/* Bit  6:	Carrier Ext Error */
#define PHY_B_PES_BAD_SSD	(1<<5)	/* Bit  5:	Bad SSD */
#define PHY_B_PES_BAD_ESD	(1<<4)	/* Bit  4:	Bad ESD */
#define PHY_B_PES_RX_ER		(1<<3)	/* Bit  3:	Receive Error */
#define PHY_B_PES_TX_ER		(1<<2)	/* Bit  2:	Transmit Error */
#define PHY_B_PES_LOCK_ER	(1<<1)	/* Bit  1:	Lock Error */
#define PHY_B_PES_MLT3_ER	(1<<0)	/* Bit  0:	MLT3 code Error */

/*****  PHY_BCOM_FC_CTR		16 bit r/w	False Carrier Counter *****/
									/* Bit 15..8:	reserved */
#define PHY_B_FC_CTR		0xff	/* Bit  7..0:	False Carrier Counter */

/*****  PHY_BCOM_RNO_CTR	16 bit r/w	Receive NOT_OK Counter *****/
#define PHY_B_RC_LOC_MSK	0xff00	/* Bit 15..8:	Local Rx NOT_OK cnt */
#define PHY_B_RC_REM_MSK	0x00ff	/* Bit  7..0:	Remote Rx NOT_OK cnt */

/*****  PHY_BCOM_AUX_CTRL	16 bit r/w	Auxiliary Control Reg *****/
#define PHY_B_AC_L_SQE		(1<<15)	/* Bit 15:	Low Squelch */
#define PHY_B_AC_LONG_PACK	(1<<14)	/* Bit 14:	Rx Long Packets */
#define PHY_B_AC_ER_CTRL	(3<<12)	/* Bit 13..12:	Edgerate Control */
									/* Bit 11:	reserved */
#define PHY_B_AC_TX_TST		(1<<10) /* Bit 10:	Tx test bit, always 1 */
									/* Bit  9.. 8:	reserved */
#define PHY_B_AC_DIS_PRF	(1<<7)	/* Bit  7:	dis part resp filter */
									/* Bit  6:	reserved */
#define PHY_B_AC_DIS_PM		(1<<5)	/* Bit  5:	dis power management */
									/* Bit  4:	reserved */
#define PHY_B_AC_DIAG		(1<<3)	/* Bit  3:	Diagnostic Mode */
									/* Bit  2.. 0:	reserved */

/*****  PHY_BCOM_AUX_STAT	16 bit r/o	Auxiliary Status Reg *****/
#define PHY_B_AS_AN_C		(1<<15)	/* Bit 15:	AutoNeg complete */
#define PHY_B_AS_AN_CA		(1<<14)	/* Bit 14:	AN Complete Ack */
#define PHY_B_AS_ANACK_D	(1<<13)	/* Bit 13:	AN Ack Detect */
#define PHY_B_AS_ANAB_D		(1<<12)	/* Bit 12:	AN Ability Detect */
#define PHY_B_AS_NPW		(1<<11)	/* Bit 11:	AN Next Page Wait */
#define PHY_B_AS_AN_RES_MSK	(7<<8)	/* Bit 10..8:	AN HDC */