📄 omap.h
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///////////////////////////////////////////////////////////////////////////////
// GPIO Interfaces.
///////////////////////////////////////////////////////////////////////////////
#define GPIO0_BASE 0xfffce000 // ARM GPIO Controller (Gigacell)
#define ARMIO_BASE 0xfffb5000 // ARM/KBD I/O Controller (ARMIO)
// ARMIO register offsets.
#define ARMIO_INPUT_LATCH_OFFSET 0x00
#define ARMIO_OUTPUT_REG_OFFSET 0x04
#define ARMIO_IO_CONTROL_OFFSET 0x08
#define ARMIO_ARM_IOCNTL_OFFSET 0x0c
#define ARMIO_KBD_ROW_LATCH_OFFSET 0x10
#define ARMIO_KBD_COL_LATCH_OFFSET 0x14
#define ARMIO_EVENT_MODE_OFFSET 0x18
#define ARMIO_IO_INT_EDGE_OFFSET 0x1c
#define ARMIO_KBD_INT_STAT_OFFSET 0x20
#define ARMIO_IO_INT_STAT_OFFSET 0x24
#define ARMIO_KBD_INT_MASK_OFFSET 0x28
#define ARMIO_IO_INT_MASK_OFFSET 0x2c
#define ARMIO_IO_DEB_TIME_OFFSET 0x30
#define ARMIO_IO_DEB_LATCH_OFFSET 0x34
// GPIO register offsets.
#define GPIO_INPUT_LATCH_OFFSET 0x00
#define GPIO_OUTPUT_REG_OFFSET 0x04
#define GPIO_IO_CONTROL_OFFSET 0x08
#define GPIO_IO_INT_EDGE_OFFSET 0x0c
#define GPIO_IO_INT_MASK_OFFSET 0x10
#define GPIO_IO_INT_STAT_OFFSET 0x14
#define GPIO_PIN_CONTROL_OFFSET 0x18
//Helen GPIO
#define GPIO0_BASE 0xfffce000 // ARM GPIO Controller 0 (Gigacell).
#define GPIO1_BASE 0xfffbc800 // ARM GPIO Controller 1 (MPUIO_1).
#define GPIO2_BASE 0xfffbd000 // ARM GPIO Controller 2 (MPUIO_2).
#define GPIO3_BASE 0xfffbd800 // ARM GPIO Controller 3 (MPUIO_3).
//Perseus GPIO is called MPUIO
#define MPUIO1_BASE 0xfffce000 // ARM GPIO Controller 1 (MPUIO_1).
#define MPUIO2_BASE 0xfffbc800 // ARM GPIO Controller 2 (MPUIO_2).
#define MPUIO3_BASE 0xfffbd000 // ARM GPIO Controller 3 (MPUIO_3).
#define MPUIO4_BASE 0xfffbd800 // ARM GPIO Controller 4 (MPUIO_4).
#define MPUIO5_BASE 0xfffbe000 // ARM GPIO Controller 5 (MPUIO_5).
#define MPUIO6_BASE 0xfffbe800 // ARM GPIO Controller 6 (MPUIO_6).
// GPIO register offsets.
#define GPIO_INPUT_LATCH_OFFSET 0x00
#define GPIO_OUTPUT_REG_OFFSET 0x04
#define GPIO_IO_CONTROL_OFFSET 0x08
#define GPIO_IO_INT_EDGE_OFFSET 0x0c
#define GPIO_IO_INT_MASK_OFFSET 0x10
#define GPIO_IO_INT_STAT_OFFSET 0x14
///////////////////////////////////////////////////////////////////////////////
// USB Client Interfaces.
///////////////////////////////////////////////////////////////////////////////
#define USB_CLIENT_BASE 0xfffb4000
//-------------------------------------------------------------------------
// USB_WFC Register Control memory offset map
//-------------------------------------------------------------------------
#define USB_REG_SIZE 4 // USB register size
#define TXDAT (0x00*USB_REG_SIZE) // Write data to transmit FIFO
#define TXSTATFLG (0x01*USB_REG_SIZE) // Status of transmit FIFO
#define TXCON1 (0x02*USB_REG_SIZE) // Configure transmit path
#define TXCON2 (0x03*USB_REG_SIZE) // Select transmit endpoint
#define RXDAT (0x04*USB_REG_SIZE) // Read data from receive FIFO
#define RXSTATFLG (0x05*USB_REG_SIZE) // Status of receive FIFO
#define RXCON1 (0x06*USB_REG_SIZE) // Configure receive path
#define RXCON2 (0x07*USB_REG_SIZE) // Select receive endpoint
#define RXFSTAT (0x08*USB_REG_SIZE) // Number of bytes in receive FIFO
#define SYSCON1 (0x09*USB_REG_SIZE) // System Configure 1
#define SYSCON2 (0x0a*USB_REG_SIZE) // System Configure 2
#define DEVSTAT (0x0b*USB_REG_SIZE) // Device status
#define SOF (0x0c*USB_REG_SIZE) // Start of frame
#define GENIE (0x10*USB_REG_SIZE) // General purpose interrupt register
#define SBIE1 (0x11*USB_REG_SIZE) // Non SOF interrupts enable 1
#define SBIE2 (0x12*USB_REG_SIZE) // Non SOF interrupts enable 2
#define SOFIE (0x13*USB_REG_SIZE) // SOF interrupt enable
#define GENI (0x14*USB_REG_SIZE) // General purpose interrupt
#define SBI1 (0x15*USB_REG_SIZE) // Non-ISO endpoints interrupt
#define SBI2 (0x16*USB_REG_SIZE) // Non-ISO endpoints interrupt
#define SOFI (0x17*USB_REG_SIZE) // Clear non-ISO endpoints interrupt
#define TXDCH0 (0x20*USB_REG_SIZE) // Transmit DMA channel 0
#define TXDCH1 (0x21*USB_REG_SIZE) // Transmit DMA channel 1
#define TXDMA1 (0x22*USB_REG_SIZE) // Transmit DMA control 1
#define TXDMA2 (0x23*USB_REG_SIZE) // Transmit DMA control 2
#define TXDMA3 (0x24*USB_REG_SIZE) // Transmit DMA control 3
#define RXDCH0 (0x28*USB_REG_SIZE) // Receive DMA channel 0
#define RXDCH1 (0x29*USB_REG_SIZE) // Receive DMA channel 1
#define RXDMA1 (0x2a*USB_REG_SIZE) // Receive DMA control 1
#define RXDMA2 (0x2b*USB_REG_SIZE) // Receive DMA control 2
#define RXDMA3 (0x2c*USB_REG_SIZE) // Receive DMA control 3
//-------------------------------------------------------------------------
/* WFC Register bit MASK */
//-------------------------------------------------------------------------
/* TXDAT register */
#define MASK_TXDAT 0x00ff
/* TXSTATFLG register */
#define MASK_Miss_In 0x4000
#define MASK_EP_Halt 0x2000
#define MASK_FIFO_En 0x1000
#define MASK_TX_Stall 0x0800
#define MASK_TX_Nak 0x0200
#define MASK_TX_Ack 0x0100
#define MASK_TXF_Empty 0x0008
/* TXCON1 register */
#define MASK_EP_Reset 0x4000
#define MASK_Set_Halt 0x2000
#define MASK_Clr_Halt 0x1000
#define MASK_TX_FEN 0x0200
#define MASK_TX_Clr 0x0080
/* TXCON2 register */
#define MASK_TX_FF_Sel 0x0010
#define MASK_TX_EP_Num 0x000f
/* RXDAT register */
#define MASK_RXDAT 0x00ff
/* RXSTATFFLG register */
#define MASK_Setup 0x8000
#define MASK_TK_NOK 0x4000
//#define MASK_EP_Halt 0x2000
//#define MASK_FIFO_En 0x1000
#define MASK_RX_Stall 0x0800
#define MASK_RX_Nak 0x0200
#define MASK_RX_Ack 0x0100
#define MASK_Data_Flush 0x0040
#define MASK_ISO_Error 0x0020
#define MASK_RXF_Empty 0x0008
#define MASK_RXF_Full 0x0004
/* RXCON1 register */
#define MASK_Clr_Setup 0x8000
//#define MASK_EP_Reset 0x4000
//#define MASK_Set_Halt 0x2000
//#define MASK_Clr_Halt 0x1000
#define MASK_Stall_Cmd 0x0800
#define MASK_RX_FEN 0x0200
#define MASK_RX_Clr 0x0080
/* RXCON2 register */
#define MASK_RX_FF_Sel 0x0010
#define MASK_RX_EP_Num 0x000f
/* RXFSTAT register */
#define MASK_RXF_Count 0x03ff
/* SYSCON1 register */
#define MASK_Nak_En 0x0200
#define MASK_Self_Pwr 0x0008
#define MASK_SOFF_En 0x0004
#define MASK_Pullup_En 0x0002
#define MASK_Low_Pwr_Dis 0x0001
/* SYSCON2 register */
#define MASK_Rmt_Wkp 0x0040
#define MASK_Dev_Conf 0x0008
/* DEVSTAT register */
#define MASK_R_Wk_OK 0x0040
#define MASK_USB_Reset 0x0020
#define MASK_SUS 0x0010
#define MASK_CFG 0x0008
#define MASK_ADD 0x0004
#define MASK_DEF 0x0002
#define MASK_ATT 0x0001
/* SOF register */
#define MASK_FT_Lock 0x1000
#define MASK_TS_OK 0x0800
#define MASK_TS 0x07ff
/* GENIE register */
#define MASK_TX1_Done_IE 0x2000
#define MASK_TX0_Done_IE 0x1000
#define MASK_RX1_Cnt_IE 0x0800
#define MASK_RX0_Cnt_IE 0x0400
#define MASK_RX1_EOT_IE 0x0200
#define MASK_RX0_EOT_IE 0x0100
#define MASK_DS_Chg_IE 0x0004
#define MASK_EP0_RX_IE 0x0002
#define MASK_EP0_TX_IE 0x0001
/* SBIE1 register */
#define MASK_EP7_RX_IE 0x8000
#define MASK_EP7_TX_IE 0x4000
#define MASK_EP6_RX_IE 0x2000
#define MASK_EP6_TX_IE 0x1000
#define MASK_EP5_RX_IE 0x0800
#define MASK_EP5_TX_IE 0x0400
#define MASK_EP4_RX_IE 0x0200
#define MASK_EP4_TX_IE 0x0100
#define MASK_EP3_RX_IE 0x0080
#define MASK_EP3_TX_IE 0x0040
#define MASK_EP2_RX_IE 0x0020
#define MASK_EP2_TX_IE 0x0010
#define MASK_EP1_RX_IE 0x0008
#define MASK_EP1_TX_IE 0x0004
/* SBIE2 register */
#define MASK_EP15_RX_IE 0x8000
#define MASK_EP15_TX_IE 0x4000
#define MASK_EP14_RX_IE 0x2000
#define MASK_EP14_TX_IE 0x1000
#define MASK_EP13_RX_IE 0x0800
#define MASK_EP13_TX_IE 0x0400
#define MASK_EP12_RX_IE 0x0200
#define MASK_EP12_TX_IE 0x0100
#define MASK_EP11_RX_IE 0x0080
#define MASK_EP11_TX_IE 0x0040
#define MASK_EP10_RX_IE 0x0020
#define MASK_EP10_TX_IE 0x0010
#define MASK_EP9_RX_IE 0x0008
#define MASK_EP9_TX_IE 0x0004
#define MASK_EP8_RX_IE 0x0002
#define MASK_EP8_TX_IE 0x0001
/* SOFIE register */
#define MASK_SOF_IE 0x0001
/* GENI register */
#define MASK_TX1_Done 0x2000
#define MASK_TX0_Done 0x1000
#define MASK_RX1_Cnt 0x0800
#define MASK_RX0_Cnt 0x0400
#define MASK_RX1_EOT 0x0200
#define MASK_RX0_EOT 0x0100
#define MASK_DS_Chg 0x0004
#define MASK_EP0_RX 0x0002
#define MASK_EP0_TX 0x0001
/* SBI1 register */
#define MASK_EP7_RX 0x8000
#define MASK_EP7_TX 0x4000
#define MASK_EP6_RX 0x2000
#define MASK_EP6_TX 0x1000
#define MASK_EP5_RX 0x0800
#define MASK_EP5_TX 0x0400
#define MASK_EP4_RX 0x0200
#define MASK_⌨️ 快捷键说明
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