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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"><html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"><title>/opentcp/arch/mb90f553a/init.c Source File</title><link href="doxygen.css" rel="stylesheet" type="text/css"></head><body><!-- Generated by Doxygen 1.2.18 --><center><a class="qindex" href="main.html">Main Page</a> <a class="qindex" href="modules.html">Modules</a> <a class="qindex" href="annotated.html">Data Structures</a> <a class="qindex" href="files.html">File List</a> <a class="qindex" href="functions.html">Data Fields</a> <a class="qindex" href="globals.html">Globals</a> <a class="qindex" href="pages.html">Related Pages</a> <a class="qindex" href="examples.html">Examples</a> </center><hr><h1>/opentcp/arch/mb90f553a/init.c</h1><a href="init_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre>00001 <span class="comment">/*</span>00002 <span class="comment"> *Copyright (c) 2000-2002 Viola Systems Ltd.</span>00003 <span class="comment"> *All rights reserved.</span>00004 <span class="comment"> *</span>00005 <span class="comment"> *Redistribution and use in source and binary forms, with or without </span>00006 <span class="comment"> *modification, are permitted provided that the following conditions </span>00007 <span class="comment"> *are met:</span>00008 <span class="comment"> *</span>00009 <span class="comment"> *1. Redistributions of source code must retain the above copyright </span>00010 <span class="comment"> *notice, this list of conditions and the following disclaimer.</span>00011 <span class="comment"> *</span>00012 <span class="comment"> *2. Redistributions in binary form must reproduce the above copyright </span>00013 <span class="comment"> *notice, this list of conditions and the following disclaimer in the </span>00014 <span class="comment"> *documentation and/or other materials provided with the distribution.</span>00015 <span class="comment"> *</span>00016 <span class="comment"> *3. The end-user documentation included with the redistribution, if </span>00017 <span class="comment"> *any, must include the following acknowledgment:</span>00018 <span class="comment"> * "This product includes software developed by Viola </span>00019 <span class="comment"> * Systems (http://www.violasystems.com/)."</span>00020 <span class="comment"> *</span>00021 <span class="comment"> *Alternately, this acknowledgment may appear in the software itself, </span>00022 <span class="comment"> *if and wherever such third-party acknowledgments normally appear.</span>00023 <span class="comment"> *</span>00024 <span class="comment"> *4. The names "OpenTCP" and "Viola Systems" must not be used to </span>00025 <span class="comment"> *endorse or promote products derived from this software without prior </span>00026 <span class="comment"> *written permission. For written permission, please contact </span>00027 <span class="comment"> *opentcp@opentcp.org.</span>00028 <span class="comment"> *</span>00029 <span class="comment"> *5. Products derived from this software may not be called "OpenTCP", </span>00030 <span class="comment"> *nor may "OpenTCP" appear in their name, without prior written </span>00031 <span class="comment"> *permission of the Viola Systems Ltd.</span>00032 <span class="comment"> *</span>00033 <span class="comment"> *THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED </span>00034 <span class="comment"> *WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF </span>00035 <span class="comment"> *MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. </span>00036 <span class="comment"> *IN NO EVENT SHALL VIOLA SYSTEMS LTD. OR ITS CONTRIBUTORS BE LIABLE </span>00037 <span class="comment"> *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR </span>00038 <span class="comment"> *CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF </span>00039 <span class="comment"> *SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR </span>00040 <span class="comment"> *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, </span>00041 <span class="comment"> *WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE </span>00042 <span class="comment"> *OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, </span>00043 <span class="comment"> *EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>00044 <span class="comment"> *====================================================================</span>00045 <span class="comment"> *</span>00046 <span class="comment"> *OpenTCP is the unified open source TCP/IP stack available on a series </span>00047 <span class="comment"> *of 8/16-bit microcontrollers, please see <http://www.opentcp.org>.</span>00048 <span class="comment"> *</span>00049 <span class="comment"> *For more information on how to network-enable your devices, or how to </span>00050 <span class="comment"> *obtain commercial technical support for OpenTCP, please see </span>00051 <span class="comment"> *<http://www.violasystems.com/>.</span>00052 <span class="comment"> */</span>00053 00069 <span class="preprocessor">#include <inet/arch/mb90f553a/mb90550.h></span>00070 <span class="preprocessor">#include <<a class="code" href="datatypes_8h.html">inet/datatypes.h</a>></span>00071 00072 00073 <span class="keywordtype">void</span> init (<span class="keywordtype">void</span>)00074 {00075 00079 <span class="comment">/* Port 0 */</span>00080 00081 DDR0 = 0x9F; <span class="comment">/* Direction. 1=O, 0=I */</span>00082 PDR0 = 0x00; <span class="comment">/* State */</span>00083 RDR0 = 0x00; <span class="comment">/* Internal Pull-Up states */</span>00084 00085 <span class="comment">/* Port 1 */</span>00086 00087 DDR1 = 0x00;00088 PDR1 = 0x00;00089 RDR1 = 0xFF;00090 00091 <span class="comment">/* Port 2 */</span>00092 00093 DDR2 = 0xFF;00094 PDR2 = 0xFF;00095 00096 <span class="comment">/* Port 3 */</span>00097 00098 DDR3 = 0xBF;00099 PDR3 = 0x80;00100 00101 <span class="comment">/* Port 4 */</span>00102 00103 DDR4 = 0xF3;00104 PDR4 = 0x10;00105 00106 <span class="comment">/* Port 5 */</span>00107 00108 PDR5 = 0x00;00109 00110 <span class="comment">/* Port 6 */</span>00111 00112 DDR6 = 0xFF;00113 PDR6 = 0x00;00114 00115 <span class="comment">/* Port 7 */</span>00116 00117 DDR7 = 0xFF;00118 PDR7 = 0x00;00119 00120 <span class="comment">/* Port 8 */</span>00121 00122 DDR8 = 0x8E;00123 PDR8 = 0x0C;00124 00125 <span class="comment">/* Port 9 */</span>00126 00127 DDR9 = 0xFF;00128 PDR9 = 0x00;00129 00130 <span class="comment">/* Port A */</span>00131 00132 DDRA = 0x0F;00133 PDRA = 0x00; 00134 00135 00136 <span class="comment">/* Initialize 16 bit reload tmr 1 for slow 10 ms step SW timers */</span>00137 00138 TMRLR1 = 2500; <span class="comment">/* 10 ms interrupt interval @ 4us step */</span>00139 00140 TMCSR1_CSL1 = 1; <span class="comment">/* 4 us step @ 8MHz input clock */</span>00141 TMCSR1_CSL0 = 0;00142 TMCSR1_MOD2 = 0; <span class="comment">/* Disable trigger from external pin */</span>00143 TMCSR1_MOD1 = 0;00144 TMCSR1_MOD0 = 0;00145 TMCSR1_OUTE = 0; <span class="comment">/* Timer output pin disabled */</span>00146 TMCSR1_OUTL = 0; <span class="comment">/* Output level (Don't care) */</span>00147 TMCSR1_RELD = 1; <span class="comment">/* Enable reload operation */</span>00148 TMCSR1_INTE = 1; <span class="comment">/* Enable interrupt request */</span>00149 TMCSR1_CNTE = 1; <span class="comment">/* Enable counting from trigger */</span>00150 TMCSR1_TRG = 1; <span class="comment">/* Trigger it! */</span> 00151 00152 <span class="comment">/* Initialize 16 bit reload tmr 0 for UART clock (used on speed 38400) */</span>00153 00154 TMRLR0 = 0;00155 TMCSR0_CSL1 = 0; <span class="comment">/* Divide PLL clock by 2 */</span>00156 TMCSR0_CSL0 = 0;00157 TMCSR0_MOD2 = 0; <span class="comment">/* Disable trigger from external pin */</span>00158 TMCSR0_MOD1 = 0;00159 TMCSR0_MOD0 = 0;00160 TMCSR0_OUTE = 0; <span class="comment">/* Timer output pin disabled */</span>00161 TMCSR0_OUTL = 0; <span class="comment">/* Output level (Don't care) */</span>00162 TMCSR0_RELD = 1; <span class="comment">/* Enable reload operation */</span>00163 TMCSR0_CNTE = 0; <span class="comment">/* Disable counting untill we need it */</span>00164 00165 00166 <span class="comment">/* Initialize the time-base timer for fast 1ms interrupt for system timer */</span>00167 <span class="comment">/* This timer is not affected by PLL and clocks always on oscillation clock */</span>00168 00169 TBTC_TBOF = 0; <span class="comment">/* Clear the request */</span>00170 TBTC_TBC1 = 0; <span class="comment">/* 1.024 ms interrupt interval @ 4 MHz */</span>00171 TBTC_TBC0 = 0;00172 TBTC_TBIE = 1; <span class="comment">/* Enable interrupt request */</span>00173 00174 00175 <span class="comment">/* Initialize serial port */</span>00176 00177 CDCR_MD = 1; <span class="comment">/* Enable communication prescaler */</span>00178 00179 CDCR_DIV3 = 1; <span class="comment">/* Set port to 9600,8,N,1 */</span>00180 CDCR_DIV2 = 1;00181 CDCR_DIV1 = 0;00182 CDCR_DIV0 = 0;00183 SMR_CS2 = 0;00184 SMR_CS1 = 0;00185 SMR_CS0 = 0;00186 SMR_SCKE = 0;00187 00188 SMR_MD1 = 0; <span class="comment">/* Asynchronous normal mode */</span>00189 SMR_MD0 = 0;00190 SMR_SOE = 1; <span class="comment">/* Enable TX pin */</span>00191 SCR_RXE = 1; <span class="comment">/* Enable RX */</span>00192 SCR_TXE = 1; <span class="comment">/* Enable TX */</span>00193 SCR_PEN = 0;00194 SCR_P = 0;00195 SCR_SBL = 0;00196 SCR_CL = 1;00197 SCR_AD = 0;00198 SCR_REC = 0;00199 00200 SSR_RIE = 0; <span class="comment">/* Disable RX Interrupt request */</span>00201 SSR_TIE = 0; <span class="comment">/* Disable TX Interrupt request */</span>00202 00203 <span class="comment">/* Kick WD */</span>00204 00205 WDTC_WTE=0;00206 00207 }00208 </pre></div><hr><address style="align: right;"><small>Generated on Sun Aug 3 20:32:59 2003 for OpenTCP by<a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border=0 width=110 height=53></a>1.2.18 </small></address></body></html>⌨️ 快捷键说明
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