📄 io_map.h
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#define PTEDD _PTEDD.Byte
#define PTEDD_PTEDD0 _PTEDD.Bits.PTEDD0
#define PTEDD_PTEDD1 _PTEDD.Bits.PTEDD1
#define PTEDD_PTEDD2 _PTEDD.Bits.PTEDD2
#define PTEDD_PTEDD3 _PTEDD.Bits.PTEDD3
#define PTEDD_PTEDD4 _PTEDD.Bits.PTEDD4
#define PTEDD_PTEDD5 _PTEDD.Bits.PTEDD5
#define PTEDD_PTEDD _PTEDD.MergedBits.grpPTEDD
#define PTEDD_PTEDD0_MASK 0x01
#define PTEDD_PTEDD1_MASK 0x02
#define PTEDD_PTEDD2_MASK 0x04
#define PTEDD_PTEDD3_MASK 0x08
#define PTEDD_PTEDD4_MASK 0x10
#define PTEDD_PTEDD5_MASK 0x20
#define PTEDD_PTEDD_MASK 0x3F
#define PTEDD_PTEDD_BITNUM 0x00
/*** IRQSC - Interrupt Request Status and Control Register; 0x00000014 ***/
typedef union {
byte Byte;
struct {
byte IRQMOD :1; /* IRQ Detection Mode */
byte IRQIE :1; /* IRQ Interrupt Enable */
byte IRQACK :1; /* IRQ Acknowledge */
byte IRQF :1; /* IRQ Flag */
byte IRQPE :1; /* IRQ Pin Enable */
byte IRQEDG :1; /* Interrupt Request (IRQ) Edge Select */
byte :1;
byte :1;
} Bits;
} IRQSCSTR;
extern volatile IRQSCSTR _IRQSC @0x00000014;
#define IRQSC _IRQSC.Byte
#define IRQSC_IRQMOD _IRQSC.Bits.IRQMOD
#define IRQSC_IRQIE _IRQSC.Bits.IRQIE
#define IRQSC_IRQACK _IRQSC.Bits.IRQACK
#define IRQSC_IRQF _IRQSC.Bits.IRQF
#define IRQSC_IRQPE _IRQSC.Bits.IRQPE
#define IRQSC_IRQEDG _IRQSC.Bits.IRQEDG
#define IRQSC_IRQMOD_MASK 0x01
#define IRQSC_IRQIE_MASK 0x02
#define IRQSC_IRQACK_MASK 0x04
#define IRQSC_IRQF_MASK 0x08
#define IRQSC_IRQPE_MASK 0x10
#define IRQSC_IRQEDG_MASK 0x20
/*** KBI1SC - KBI1 Status and Control; 0x00000016 ***/
typedef union {
byte Byte;
struct {
byte KBIMOD :1; /* Keyboard Detection Mode */
byte KBIE :1; /* Keyboard Interrupt Enable */
byte KBACK :1; /* Keyboard Interrupt Acknowledge */
byte KBF :1; /* Keyboard Interrupt Flag */
byte KBEDG4 :1; /* Keyboard Edge Select for Port A Bit 4 */
byte KBEDG5 :1; /* Keyboard Edge Select for Port A Bit 5 */
byte KBEDG6 :1; /* Keyboard Edge Select for Port A Bit 6 */
byte KBEDG7 :1; /* Keyboard Edge Select for Port A Bit 7 */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte grpKBEDG_4 :4;
} MergedBits;
} KBI1SCSTR;
extern volatile KBI1SCSTR _KBI1SC @0x00000016;
#define KBI1SC _KBI1SC.Byte
#define KBI1SC_KBIMOD _KBI1SC.Bits.KBIMOD
#define KBI1SC_KBIE _KBI1SC.Bits.KBIE
#define KBI1SC_KBACK _KBI1SC.Bits.KBACK
#define KBI1SC_KBF _KBI1SC.Bits.KBF
#define KBI1SC_KBEDG4 _KBI1SC.Bits.KBEDG4
#define KBI1SC_KBEDG5 _KBI1SC.Bits.KBEDG5
#define KBI1SC_KBEDG6 _KBI1SC.Bits.KBEDG6
#define KBI1SC_KBEDG7 _KBI1SC.Bits.KBEDG7
#define KBI1SC_KBEDG_4 _KBI1SC.MergedBits.grpKBEDG_4
#define KBI1SC_KBEDG KBI1SC_KBEDG_4
#define KBI1SC_KBIMOD_MASK 0x01
#define KBI1SC_KBIE_MASK 0x02
#define KBI1SC_KBACK_MASK 0x04
#define KBI1SC_KBF_MASK 0x08
#define KBI1SC_KBEDG4_MASK 0x10
#define KBI1SC_KBEDG5_MASK 0x20
#define KBI1SC_KBEDG6_MASK 0x40
#define KBI1SC_KBEDG7_MASK 0x80
#define KBI1SC_KBEDG_4_MASK 0xF0
#define KBI1SC_KBEDG_4_BITNUM 0x04
/*** KBI1PE - KBI1 Pin Enable Register; 0x00000017 ***/
typedef union {
byte Byte;
struct {
byte KBIPE0 :1; /* Keyboard Pin Enable for Port A Bit 0 */
byte KBIPE1 :1; /* Keyboard Pin Enable for Port A Bit 1 */
byte KBIPE2 :1; /* Keyboard Pin Enable for Port A Bit 2 */
byte KBIPE3 :1; /* Keyboard Pin Enable for Port A Bit 3 */
byte KBIPE4 :1; /* Keyboard Pin Enable for Port A Bit 4 */
byte KBIPE5 :1; /* Keyboard Pin Enable for Port A Bit 5 */
byte KBIPE6 :1; /* Keyboard Pin Enable for Port A Bit 6 */
byte KBIPE7 :1; /* Keyboard Pin Enable for Port A Bit 7 */
} Bits;
} KBI1PESTR;
extern volatile KBI1PESTR _KBI1PE @0x00000017;
#define KBI1PE _KBI1PE.Byte
#define KBI1PE_KBIPE0 _KBI1PE.Bits.KBIPE0
#define KBI1PE_KBIPE1 _KBI1PE.Bits.KBIPE1
#define KBI1PE_KBIPE2 _KBI1PE.Bits.KBIPE2
#define KBI1PE_KBIPE3 _KBI1PE.Bits.KBIPE3
#define KBI1PE_KBIPE4 _KBI1PE.Bits.KBIPE4
#define KBI1PE_KBIPE5 _KBI1PE.Bits.KBIPE5
#define KBI1PE_KBIPE6 _KBI1PE.Bits.KBIPE6
#define KBI1PE_KBIPE7 _KBI1PE.Bits.KBIPE7
#define KBI1PE_KBIPE0_MASK 0x01
#define KBI1PE_KBIPE1_MASK 0x02
#define KBI1PE_KBIPE2_MASK 0x04
#define KBI1PE_KBIPE3_MASK 0x08
#define KBI1PE_KBIPE4_MASK 0x10
#define KBI1PE_KBIPE5_MASK 0x20
#define KBI1PE_KBIPE6_MASK 0x40
#define KBI1PE_KBIPE7_MASK 0x80
/*** SCI1BD - SCI1 Baud Rate Register; 0x00000018 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** SCI1BDH - SCI1 Baud Rate Register High; 0x00000018 ***/
union {
byte Byte;
struct {
byte SBR8 :1; /* Baud Rate Modulo Divisor Bit 8 */
byte SBR9 :1; /* Baud Rate Modulo Divisor Bit 9 */
byte SBR10 :1; /* Baud Rate Modulo Divisor Bit 10 */
byte SBR11 :1; /* Baud Rate Modulo Divisor Bit 11 */
byte SBR12 :1; /* Baud Rate Modulo Divisor Bit 12 */
byte :1;
byte :1;
byte :1;
} Bits;
struct {
byte grpSBR_8 :5;
byte :1;
byte :1;
byte :1;
} MergedBits;
} SCI1BDHSTR;
#define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte
#define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8
#define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9
#define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10
#define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11
#define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12
#define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8
#define SCI1BDH_SBR SCI1BDH_SBR_8
#define SCI1BDH_SBR8_MASK 0x01
#define SCI1BDH_SBR9_MASK 0x02
#define SCI1BDH_SBR10_MASK 0x04
#define SCI1BDH_SBR11_MASK 0x08
#define SCI1BDH_SBR12_MASK 0x10
#define SCI1BDH_SBR_8_MASK 0x1F
#define SCI1BDH_SBR_8_BITNUM 0x00
/*** SCI1BDL - SCI1 Baud Rate Register Low; 0x00000019 ***/
union {
byte Byte;
struct {
byte SBR0 :1; /* Baud Rate Modulo Divisor Bit 0 */
byte SBR1 :1; /* Baud Rate Modulo Divisor Bit 1 */
byte SBR2 :1; /* Baud Rate Modulo Divisor Bit 2 */
byte SBR3 :1; /* Baud Rate Modulo Divisor Bit 3 */
byte SBR4 :1; /* Baud Rate Modulo Divisor Bit 4 */
byte SBR5 :1; /* Baud Rate Modulo Divisor Bit 5 */
byte SBR6 :1; /* Baud Rate Modulo Divisor Bit 6 */
byte SBR7 :1; /* Baud Rate Modulo Divisor Bit 7 */
} Bits;
} SCI1BDLSTR;
#define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte
#define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0
#define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1
#define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2
#define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3
#define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4
#define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5
#define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6
#define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7
#define SCI1BDL_SBR0_MASK 0x01
#define SCI1BDL_SBR1_MASK 0x02
#define SCI1BDL_SBR2_MASK 0x04
#define SCI1BDL_SBR3_MASK 0x08
#define SCI1BDL_SBR4_MASK 0x10
#define SCI1BDL_SBR5_MASK 0x20
#define SCI1BDL_SBR6_MASK 0x40
#define SCI1BDL_SBR7_MASK 0x80
} Overlap_STR;
} SCI1BDSTR;
extern volatile SCI1BDSTR _SCI1BD @0x00000018;
#define SCI1BD _SCI1BD.Word
/*** SCI1C1 - SCI1 Control Register 1; 0x0000001A ***/
typedef union {
byte Byte;
struct {
byte PT :1; /* Parity Type */
byte PE :1; /* Parity Enable */
byte ILT :1; /* Idle Line Type Select */
byte WAKE :1; /* Receiver Wakeup Method Select */
byte M :1; /* 9-Bit or 8-Bit Mode Select */
byte RSRC :1; /* Receiver Source Select */
byte SCISWAI :1; /* SCI Stops in Wait Mode */
byte LOOPS :1; /* Loop Mode Select */
} Bits;
} SCI1C1STR;
extern volatile SCI1C1STR _SCI1C1 @0x0000001A;
#define SCI1C1 _SCI1C1.Byte
#define SCI1C1_PT _SCI1C1.Bits.PT
#define SCI1C1_PE _SCI1C1.Bits.PE
#define SCI1C1_ILT _SCI1C1.Bits.ILT
#define SCI1C1_WAKE _SCI1C1.Bits.WAKE
#define SCI1C1_M _SCI1C1.Bits.M
#define SCI1C1_RSRC _SCI1C1.Bits.RSRC
#define SCI1C1_SCISWAI _SCI1C1.Bits.SCISWAI
#define SCI1C1_LOOPS _SCI1C1.Bits.LOOPS
#define SCI1C1_PT_MASK 0x01
#define SCI1C1_PE_MASK 0x02
#define SCI1C1_ILT_MASK 0x04
#define SCI1C1_WAKE_MASK 0x08
#define SCI1C1_M_MASK 0x10
#define SCI1C1_RSRC_MASK 0x20
#define SCI1C1_SCISWAI_MASK 0x40
#define SCI1C1_LOOPS_MASK 0x80
/*** SCI1C2 - SCI1 Control Register 2; 0x0000001B ***/
typedef union {
byte Byte;
struct {
byte SBK :1; /* Send Break */
byte RWU :1; /* Receiver Wakeup Control */
byte RE :1; /* Receiver Enable */
byte TE :1; /* Transmitter Enable */
byte ILIE :1; /* Idle Line Interrupt Enable (for IDLE) */
byte RIE :1; /* Receiver Interrupt Enable (for RDRF) */
byte TCIE :1; /* Transmission Complete Interrupt Enable (for TC) */
byte TIE :1; /* Transmit Interrupt Enable (for TDRE) */
} Bits;
} SCI1C2STR;
extern volatile SCI1C2STR _SCI1C2 @0x0000001B;
#define SCI1C2 _SCI1C2.Byte
#define SCI1C2_SBK _SCI1C2.Bits.SBK
#define SCI1C2_RWU _SCI1C2.Bits.RWU
#define SCI1C2_RE _SCI1C2.Bits.RE
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