a86_reg_calc_mux.v

intel 8088 架构的verilog代码

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_reg_calc_mux(
  rst,clk,
  icode,
  ip,sp,bp,
  si,di,
  cs,ds,ss,es,
  ax,bx,cx,dx,
  din,dout,
  a
);

input rst;
input clk;
input [`a86_icode_width-1:0] icode;

wire rst;
wire clk;


input [15:0] ip;
wire [15:0] ip;

input [15:0] sp;
wire [15:0] sp;

input [15:0] bp;
wire [15:0] bp;

input [15:0] si;
wire [15:0] si;

input [15:0] di;
wire [15:0] di;

input [15:0] cs;
wire [15:0] cs;
input [15:0] ds;
wire [15:0] ds;
input [15:0] ss;
wire [15:0] ss;
input [15:0] es;
wire [15:0] es;

input [15:0] ax;
wire [15:0] ax;
input [15:0] bx;
wire [15:0] bx;
input [15:0] cx;
wire [15:0] cx;
input [15:0] dx;
wire [15:0] dx;

output [15:0] dout;
wire [15:0] dout;

output [19:0] a;
wire [19:0] a;

input [31:0] din;
wire [31:0] din;



wire [15:0] segment;
wire [15:0] offset;
wire [15:0] ea;


a86_seg_sel a86_seg_sel_0 (
    .sel( 2'b01 ), 
    .cs( cs ), 
    .ds( ds ), 
    .ss( ss ), 
    .es( es ), 
    .seg( segment )
    );

a86_reg_sel a86_reg_sel_0 (
    .icode(icode),
    .rm( 3'b000 ), 
    .w( 1'b0 ), 
    .ax( ax ), 
    .cx( cx ), 
    .dx( dx ), 
    .bx( bx ), 
    .sp( sp ), 
    .bp( bp ), 
    .si( si ), 
    .di( di ), 
    .dout( dout )
    );

a86_ea_calc a86_ea_calc_0 (
    .ea( ea ), 
    .bx( bx ), 
    .bp( bp ), 
    .di( di ), 
    .si( si ), 
    .disp( icode[`a86_icode_i_start+15+16:`a86_icode_i_start+16] ), 
    // r/m field
    .rm( icode[`a86_icode_i_start+2+8:`a86_icode_i_start+8] ),
    // mode?
    .mode( icode[`a86_icode_i_start+7+8:`a86_icode_i_start+6+8] )
    );

a86_offset_sel a86_offset_sel_0 (
    .sel( 2'b00 ), 
    .ea( ea ), 
    .sp( sp ), 
    .ip( ip ), 
    .offset( offset )
    );

a86_pag a86_pag_0 (
    .seg_base( segment ), 
    .offset( offset ), 
    .pa( a )
    );


endmodule