a86_bp_reg.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 23 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"

module a86_bp_reg(rst,clk,we,din,bp);

input rst;
input clk;
input we;
input [15:0] din;
output [15:0] bp;

// latches
reg [15:0] bp; 


// Latch writes to bp reg
always @ (posedge clk)
  if (rst) bp <= 16'hB000;
  else if (we) bp <= din;

endmodule