u26a_clk.sp

ddr2控制器一些源码

*                          MICRON HSPICE MODEL
*
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*               Copyright 2005 Micron Technology, Inc. All rights reserved.
*
*************** 64Megx4, 32Megx8, 16Megx16 DDR2-400/533 SDRAM *****************
**************** Example HSPICE setup for CLK/CLK# inputs**********************

***********************************************************
****             ___                                      *
****    CLK_OUT-/  +|-CLKPAD----\/\/\/--@@@@-----IN_PKG   *
****           {   -|-CLKPAD_--| R_pkg  L_pkg |           *
****   CLK_OUT_-\___|-RCVREN   |             ===C_pkg     *
****                           |              |           *
****                           |             GND          *
****                           |                          *
****                           -\/\/\/--@@@@-----INN_PKG  *
****                            Rn_pkg Ln_pkg |           *
****                                         ===Cn_pkg    *
****                                          |           *
****                                         GND          *
***********************************************************

**** This netlist is for the x4, x8, x16 256Mb DDR2-400/533 SDRAM **********
**** The input signals are IN_PKG and INN_PKG.
**** The positive output of the input receiver circuit is the node CLK_OUT.
**** The negative output of the input receiver circuit is the node CLK_OUT_.
**** To account for package parasitics correlative impedance values
**** (netlist elements r_pkg,l_pkg,c_pkg for CLKPAD, rn_pkg,ln_pkg,cn_pkg
**** for CLKPAD_) have been attached to the PAD nodes.

**** The .LIB statement selects the following modes:
****    TT - Typical N, Typical P, Typical die capacitance
****    SS - Slow N, Slow P, Maximum die capacitance
****    FF - Fast N, Fast P, Minimum die capacitance

**** To run this simulation, the files "model.cnr" and "u26a_clkbuff.inc" are
**** required to be in the same directory as this netlist.
**** Temperature settings are: Typical 40C, Slow 100C, Fast 0C

.OPTIONS ACCT OPTS NOPAGE POST
.OPTIONS METHOD=GEAR
.OPTIONS SEARCH=' '  $This option must be present for decryption to work

.TRAN 0.05ns 10.0ns
**The temperature is for the slow case
.TEMP 100
.LIB "model.cnr" SS

**** Input signals and power supplies setup
**** Note: vccp is a regulated internal voltage
**** Match up typ, min, or max voltages for corner sims
.PARAM  vcc_typ   = 1.800V
.PARAM  vcc_min   = 1.700V
.PARAM  vcc_max   = 1.900V

.PARAM  vccp_typ  = 3.30V
.PARAM  vccp_min  = 3.20V
.PARAM  vccp_max  = 3.40V

.PARAM  gnd       = 0.0V
********************************************************************************
.PARAM  vcc       = vcc_min
.PARAM  vccp      = vccp_min
******************************************************************************** 
Vvcc    vcc   0  DC = vcc
Vvccp   vccp  0  DC = vccp

Ven  rcvr_en   0  DC = vcc
**Active high receiver enable

Vin   in_pkg  0  PULSE gnd vcc 100ps 200ps 200ps 2.30ns 5.00ns
**Vin toggles the CLK at 200MHz
Vin_  inn_pkg 0  PULSE vcc gnd 100ps 200ps 200ps 2.30ns 5.00ns

* top cell:  clk
* *********************************************
* Output load circuits:
xi0 clkpad clkpad_ rcvr_en clk_out gnd vcc u26a_clkbuff

* Refer to the IBIS model for specific package parasitic values.
r_pkg clkpad net1 R=56.5e-3
l_pkg net1 in_pkg L=1.96e-9
c_pkg in_pkg gnd c=270e-15
rn_pkg clkpad_ net2 R=56.5e-3
ln_pkg net2 inn_pkg L=1.96e-9
cn_pkg inn_pkg gnd c=270e-15


.alter typ
.PARAM  vcc         = vcc_typ
.PARAM  vccp        = vccp_typ
.temp 40
.LIB "model.cnr" TT

.alter fast
.PARAM  vcc         = vcc_max
.PARAM  vccp        = vccp_max
.temp 0
.LIB "model.cnr" FF

.END